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Superconductor Science and Technology

A high-speed superconducting digital autocorrelator operating at 20.48 GHz

Steven B. Kaplan, Henrik Engseth

Published Oct 18, 2007• 14 citations
Publisher

Abstract

Digital autocorrelators have a number of applications, such as in astronomical observation in the terahertz range, and for spectrum monitoring over wide radiofrequency bands. We have simulated, designed and tested a 16-lag superconducting digital autocorrelator circuits with parallel and also with serial data outputs. By using a novel clock line and a target critical current density of 4.5 kA cm^−2, we have successfully tested this digital circuit up to a clock rate of 20.48 GHz with negligible bit error rates on each lag. Moreover, this autocorrelator design can be expanded with a larger number of lags by tiling chips in a multi-chip module. We also include details of our first multi-chip design.

DOI
10.1088/0953-2048/20/11/s02

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Digital autocorrelators have a number of applications, such as in astronomical observation in the terahertz range, and for spectrum monitoring over wide radiofrequency bands. We have simulated, designed and tested a 16-lag superconducting digital autocorrelator circuits with parallel and also with serial data outputs. By using a novel clock line and a target critical current density of 4.5 kA cm^−2, we have successfully tested this digital circuit up to a clock rate of 20.48 GHz with negligible bit error rates on each lag. Moreover, this autocorrelator design can be expanded with a larger number of lags by tiling chips in a multi-chip module. We also include details of our first multi-chip design.
To improve the accuracy of astronomical data analysis, an increase in the number of output bits from the A/D converter is effective. We investigated a single-flux-quantum (SFQ) autocorrelator and an integrator that supports multiple-bit signal output from an SFQ A/D converter for astronomical data processing. The SFQ binary counter was used as the integrator that decimates the output from the SFQ autocorrelator for communication with equipment at room temperature. We designed the test circuits composed of 2-bit inputs, an autocorrelator, and an integrator that contains 5631 Josephson junctions using the 10 kA/cm2Nb process. We confirmed the correct operation of the test circuit with a normalized bias voltage margin of 102%-114% by the low-speed test. We obtained its correct high-speed operation up to a 55.1 GHz clock frequency. In terms of circuit design, scaling up the test circuit is easy. These results indicate the effectiveness of a high-precision and large-bandwidth radio astronomical observation using SFQ circuit technology.
We present the results of low- and high-speed testing of a fully integrated all-digital one-bit RSFQ autocorrelator for short-millimeter and submillimeter wave spectrometry applications. The 16-channel device, complete with a 16/spl times/9 array of binary counters, on-chip double-oversampling quantizer and on-chip clock was operational at clock speeds of up to 11 GHz. The total number of Josephson junctions in the design was 1672, while the estimated total power dissipation was less than 0.1 mW. For high-speed testing of the device we have developed a specialized 16-channel room-temperature interface capable of real-time data acquisition at a 16 Mbps-per-channel output rate. Extensive high-speed on-chip testing of the autocorrelator has also been performed, both in analog and digital modes, in the latter mode with an additional on-chip clock controller. All chips were fabricated in HYPRES' standard 3.5 /spl mu/m-10 /spl mu/A//spl mu/m/sup 2/ Nb-trilayer process. We also present a new concept of a 128-channel autocorrelator system built on 8 independent identical chips with approximately 2,500 Josephson junctions per chip, i.e. within the reach of the present-day fabrication technology.
AbstractSuperconducting digital technology based on Rapid Single Flux Quantum (RSFQ) logic offers a 50 times faster clock rate and 100 times less on chip power consumption than today's mainstream semiconductor electronics. This technology is attractive for many applications and in particular for Digital Signal Processing (DSP). The applications of the RSFQ DSPs are numerous and include multi-user detection in spread spectrum system, channel equalization for Multi-in, Multi-out (MIMO) systems, and blind detection and signal tracking for signal intelligence.At Chalmers we are developing a hybrid DSP with target performance of 30 giga operations per second. It consists of an RSFQ Multiply Accumulate unit (MAC), RSFQ fast cache memory, and an external semiconductor memory. The development of the complex high speed cryogenic digital system requires interface, packaging and testing solutions. The main difficulties are due to the 4 K operational temperature, the high magnetic field sensitivity of the RSFQ circuits, the multi-channel high bandwidth interface required in the hybrid architecture, and the high speed RSFQ digital core. The key steps towards addressing each of these problems are the subject of this thesis. The main emphasis is put on the experimental testing and interfacing of superconductor electronics. A large part of the work is connected to the experimental verification of DSP components and their incremental improvement towards functionality. The RSFQ circuits tested were fabricated using the four-metal layer VLSI processes available from NGST(8 kA/cm^2 Josephson junction critical current) and HYPRES (both 1 kA/cm^2 and HYPRES 4.5 kA/cm^2. The main results of the work are demonstrations of the RSFQ cache memory with more than 2,000 Josephson junctions, 33.5 GHz operation of the digital clock controller, and 20.48 GHz operation of the autocorrelator. In addition, various experiments have been done for investigation of parasitic effects in RSFQ circuits such as flux trapping and influence of the high current bias lines.At the final stage of the work, a unique high bandwidth 4 K cryocooler based experimental setup has been developed. The system, developed in close cooperation with Hypres Inc. USA, has 40 high speed I/Os with bandwidth of 2 Gbps, 64 DC bias channels, 4 high frequency clock lines, and 4 auxiliary control lines. It supports exchangeable test units for 10 mm x 10 mm and 20 mm x 20 mm Multi Chip Module (MCM) carriers. The availability of such a system is critical to demonstration of the hybrid DSP prototype and future commercialization.
Compact mm/submm integrated spectrometers are required for radio-astronomical research, remote monitoring of the Earth atmosphere and environmental monitoring for hazardous materials of chemical and biological origin. Assembled on a multi-chip module the all superconducting integrated spectrometer offers integration of thin film analog components such as a mixer, superconducting local oscillator and an intermediate frequency SQUID amplifier together with superconducting digital circuitry. A Rapid Single Flux Quantum (RSFQ) 128-bit autocorrelator formed by 16-bit autocorrelator and a 112-bit programmable shift register that adjusts the data delay in increments of 16, is used for digitizing of the down converted signals and real-time digital processing. Experimental results showing both operation of components and the way to their successful integration are presented.
A critical component for high bandwidth communications links is a digital switch. Desirable features of a digital switch include: high input/output bandwidth, high channel count, scalability, low latency and interchannel skew. Superconductive circuits, with simultaneous high speed and low power advantages (even including the requisite cryocooler) have been applied to a highly scaleable crossbar switch, useful in supercomputer networks, massively parallel processing (MPP), and high data rate telecommunications. We report here on the testing of a 16/spl times/16 switch chip based on the switch chip component of the highly scaleable crossbar system. We have successfully transmitted multi-Gb/s data through this superconducting switch, with packet destination addressing decoded from the header of the data packet. The data are transmitted to a separate superconducting amplifier chip, mounted on a superconducting multi-chip module with the switch. The switch is a crossbar architecture, voltage state design, and operated to beyond 3 Gb/s. The amplifier is a clocked latching stack of Josephson junctions. Output of the amplifier at 6.2 Gb/s is 7.0 mV, which facilitates the interface of the module to its users. BER of the two-chip assembly is 10/sup -9/ or less above 2 Gb/s.
We have developed an advanced version of on-chip test system with new high-speed clock generation and control. For high-speed clock generation, a novel wide-bandwidth ring generator is designed using circular Josephson transmission lines with an inductively coupled trigger. The generator is capable of producing SFQ clock pulses in the range of from 15 to 55 GHz using a 1 kA/cm/sup 2/ Nb fabrication process. For clock control, we have designed two different types of clock-controller circuits based on programmable shift-register and counter. Using the on-chip test system, we have successfully tested a parallel multiplier module up to 15 GHz with 16% dc bias margins.