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Superconductor Science and Technology

Design and implementation of circuit components of the SFQ microprocessor, CORE1

Nobuo Nakajima, Fumiya Matsuzaki, Yuki Yamanashi, Nobuyuki Yoshikawa, Masamitsu Tanaka, Takaharu Kondo, Akira Fujimaki, Hirotaka Terai, Shinichi Yorozu

Published Jan 7, 2004• 19 citations
Publisher

Abstract

We have designed, implemented and tested several circuit components of a prototype of the SFQ microprocessor, CORE1, CORE1 is a synchronously clocked 8 bit microprocessor based on a bit-serial architecture. We have designed its circuit components using a cell-based design approach and an automated top-down CAD environment. We have successfully obtained correct operations of all circuit components, including an instruction register, a program counter and a controller.

DOI
10.1088/0953-2048/17/3/001

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Superconductor Science and Technology•Oct 18, 2007•31 citations
We have designed, implemented and tested several circuit components of a prototype of the SFQ microprocessor, CORE1, CORE1 is a synchronously clocked 8 bit microprocessor based on a bit-serial architecture. We have designed its circuit components using a cell-based design approach and an automated top-down CAD environment. We have successfully obtained correct operations of all circuit components, including an instruction register, a program counter and a controller.
An eight-bit SFQ processor has been designed and some key components have been tested to confirm feasibility of the large-scale SFQ digital circuit. The designed processor is composed of a one-bit ALU, two eight-bit registers with local clock generators, an instruction register, a five-bit program counter, a state controller, and a 32-byte register file. A bit-serial architecture and a distributed local clock architecture, where each register has its own local clock generator, have been employed in order to increase the local clock frequency. The target clock frequency is 16 GHz and 10 GHz for the NEC 2.5 kA/cm/sup 2/ and Hypres 1 kA/cm/sup 2/ Nb processes. On the circuit design level, we have used a data-driven self-timed architecture and a binary decision diagram, which reduce the timing design difficulty in high frequency operation. The processor, which contains 7,300 Josephson junctions, has been designed by using a cell-based design methodology with the assistance of a top-down CAD environment. We have successfully tested some important circuit blocks, including a one-bit ALU, eight-bit registers, and a demultiplexer for register files.
Design and Implementation of a Pipelined Bit-Serial SFQ Microprocessor, CORE1β{\rm CORE}1\betaCORE1β
A pipelined 8-bit-serial single-flux-quantum (SFQ) microprocessor, called CORE1beta, was designed and tested. The CORE1beta has two cascaded arithmetic logic units (ALUs) based on forwarding architecture, which can perform two register operations from one instruction. Pipelining is also extensively adopted to enhance the performance. A new design method, known as one-hot encoding, has been introduced into the design of the control circuit. The 4-stage-pipelined SFQ microprocessors, CORE1beta8, have been implemented using the CONNECT cell library and the SRL 2.5 kA/cm2Nb process. The frequency for the instruction fetch is 25 GHz, and 20 GHz for the bit-serial data operation. The peak performance and the power consumption of the CORE1beta8 are estimated to be 1400 MOPS (million instructions per second) and 3.4 mW, respectively. We have experimentally demonstrated 4-stage pipelining and all functionalities of the CORE1beta8 microprocessors by on-chip high-speed tests.
We describe the development of single-flux-quantum (SFQ) microprocessors and the related technologies such as designing, circuit architecture, microarchitecture, etc. Since the microprocessors studied here aim for a general-purpose computing system, we employ the complexity-reduced (CORE) architecture in which the high-speed nature of the SFQ circuits is used not for increasing processor performance but for reducing the circuit complexity. The bit-serial processing is the most suitable way to realize the CORE architecture. We assembled all the best technologies concerning SFQ integrated circuits and designed the SFQ microprocessors, CORE1α, CORE1β, and CORE1γ. The CORE1β was made up of about 11000 Josephson junctions and successfully demonstrated. The peak performance reached 1400 million operations per second with a power consumption of 3.4mW. We showed that the SFQ microprocessors had an advantage in a performance density to semiconductor's ones, which lead to the potential for constructing a high performance SFQ-circuit-based computing system.
We have been developing large-scale SFQ digital circuit systems and have shown the successful demonstration of our prototype SFQ microprocessors and memories. Their circuit scale is now over several thousands of junctions. One question arising in such large SFQ circuits is whether their error rate is low enough for digital applications. In this study, we have examined the error rate of circuit components of our microprocessor. An error rate test system for a program counter (PC) of the CORE1 microprocessor was made using Nb 2.5 kA/cm/sup 2/ process. The system is composed of a clock generator, a comparator and a 16-bit PC under test. It was found from the experiment that the system error rate of the 16-bit PC is lower than 10/sup -8/, which corresponds to a bit-error-rate better than 10/sup -12/. We have also evaluated a timing jitter of the clock generator and an effective temperature of the PC based on the experimental results.
A microprocessor test vehicle was developed for the investigation of asynchronous design methodology for rapid- single-flux-quantum (RSFQ) circuits. We have designed and implemented a fully asynchronous RSFQ microprocessor, named SCRAM2. The data-driven self-timing (DDST) architecture is used for the design of circuit blocks of the SCRAM2. In order to ensure the logical ordering between the circuit blocks, bit-serial handshaking was adopted. The performance of the handshaking system was enhanced based on the scalable-delay-insensitive (SDI) model. The SCRAM2 is an 8-bit bit-serial microprocessor with three-stage pipelining, with a basic microarchitecture similar to that of our previously designed synchronous microprocessor, CORE1alpha. The estimated average performance of the SCRAM2 is 577 MIPS using a logic simulation. We have implemented all circuit components using the SRL 2.5 kA/cm2Nb process and confirmed their correct operation. Several operations of the SCRAM2 have been successfully confirmed.
A pipelined 8 bit-serial single-flux-quantum microprocessor integrating cache memories, called CORE1γ, has been designed and implemented. The CORE1γ has 16 byte and 8 byte shift-register-based cache memories for instructions and for data, respectively. The microprocessor overlaps four instructions in pipeline executions. The pipeline stages are optimized to control the cache memories and a new circuit component is developed to manage the pipeline execution according to whether each cache hits or misses. Advanced passive transmission line techniques with use of the cell library of the 2.5 kA cm −2 niobium standard process are utilized to implement the CORE1γ accompanied by extremely complex interconnects. The CORE1γ is made up of 295 passive interconnects, and 22302 Josephson junctions are integrated on a 6.36 × 6.36 mm 2 area. The logic simulation shows that the peak performance is estimated at 1000 million operations per second, and it is kept even during memory access as long as the cache memories hit.