We generalized systematically the renormalized mean field theory in the case of uniform states to the unrestricted case of general inhomogeneous states with competing spin-, charge-, and superconducting orders. Applying the theory to $\mathrm{high}\text{\ensuremath{-}}{T}_{c}$ superconductors, we discuss the issues of electronic inhomogeneity, the superfluid density, and in particular the local electron density of states. The results account for many intriguing aspects of the phenomenology.We generalized systematically the renormalized mean field theory in the case of uniform states to the unrestricted case of general inhomogeneous states with competing spin-, charge-, and superconducting orders. Applying the theory to $\mathrm{high}\text{\ensuremath{-}}{T}_{c}$ superconductors, we discuss the issues of electronic inhomogeneity, the superfluid density, and in particular the local electron density of states. The results account for many intriguing aspects of the phenomenology.

arXiv:cond-mat/0506712Physical Review BMar 17, 200642 citations

Transition and Prospects of Superconducting Integrated Electronics

Yuki Yamanashi

The Journal of the Institute of Electrical Engineers of JapanAug 31, 20230 citations

New prospects in superconductor electronics

Alexander B Zorin, K. K. Likharev, Vasili K. Semenov

Jan 1, 19890 citations

High-density superconductive logic circuits utilizing 0 and π josephson junctions

Sasan Razmkhah, Massoud Pedram

Abstract Superconductor Electronics (SCE) is a fast and power-efficient technology with great potential for overcoming conventional CMOS electronics’ scaling limits. Nevertheless, the primary challenge confronting SCE today is its integration level, which lags several orders of magnitude behind CMOS circuits. In this study, we have innovated and simulated a novel logic family grounded in the principles of phase shifts occurring in 0 and π Josephson junctions. The fast phase logic (FPL) eliminates the need for large inductor loops and shunt resistances by combining the half-flux and phase logic. Therefore, the Josephson junction (JJ) area only limits the integration density. The cells designed with this paradigm are fast, and the clock-to-Q delay for logic cells is about 4ps. While maintaining over 50% parameter margins for wiring cells. This logic is power efficient and can increase the integration by at least 100×in the SCE chips.Abstract Superconductor Electronics (SCE) is a fast and power-efficient technology with great potential for overcoming conventional CMOS electronics’ scaling limits. Nevertheless, the primary challenge confronting SCE today is its integration level, which lags several orders of magnitude behind CMOS circuits. In this study, we have innovated and simulated a novel logic family grounded in the principles of phase shifts occurring in 0 and π Josephson junctions. The fast phase logic (FPL) eliminates the need for large inductor loops and shunt resistances by combining the half-flux and phase logic. Therefore, the Josephson junction (JJ) area only limits the integration density. The cells designed with this paradigm are fast, and the clock-to-Q delay for logic cells is about 4ps. While maintaining over 50% parameter margins for wiring cells. This logic is power efficient and can increase the integration by at least 100×in the SCE chips.

arXiv:2308.12474Engineering Research ExpressFeb 9, 20249 citations

Low-Power High-Speed Hybrid Temperature Heterogeneous Technology Digital Data Link

Deepnarayan Gupta, Joseph C. Bardin, Amol Inamdar +6 more

High-speed digital data links from 4-K superconductor electronics to room temperature are challenging due to the fact that energy/bit for single flux quantum logic is many (six) orders of magnitude lower than that of standard room-temperature logic. Our approach of building an energy-efficient high-speed data link involves a joint electrical-thermal design of a temperature-distributed architecture using different electronic technologies. This differential digital data link design involves superconductor, multiple cryogenic semiconductor and additional room-temperature semiconductor circuitry. The current design involves three cryogenic semiconductor ICs for integration with a multistage cryocooled digital system. The first cryogenic semiconductor IC is designed to operate at 4 K with a power consumption of 0.3 mW and interface directly with the superconductor differential single flux quantum/dc drivers. For testing it, a superconductor carrier chip containing an analog-to-digital converter has been designed for the HYPRES dual- $J_{c}$ (4.5 and 20 $\hbox{kA/cm}^{2}$ ) fabrication process.High-speed digital data links from 4-K superconductor electronics to room temperature are challenging due to the fact that energy/bit for single flux quantum logic is many (six) orders of magnitude lower than that of standard room-temperature logic. Our approach of building an energy-efficient high-speed data link involves a joint electrical-thermal design of a temperature-distributed architecture using different electronic technologies. This differential digital data link design involves superconductor, multiple cryogenic semiconductor and additional room-temperature semiconductor circuitry. The current design involves three cryogenic semiconductor ICs for integration with a multistage cryocooled digital system. The first cryogenic semiconductor IC is designed to operate at 4 K with a power consumption of 0.3 mW and interface directly with the superconductor differential single flux quantum/dc drivers. For testing it, a superconductor carrier chip containing an analog-to-digital converter has been designed for the HYPRES dual-$J_{c}$(4.5 and 20$\hbox{kA/cm}^{2}$) fabrication process.

IEEE Transactions on Applied SuperconductivityApr 5, 201320 citations

Interfacing Superconductor and Semiconductor Digital Electronics

Yerzhan Mustafa, Selçuk Köse

Interface circuits are the key components that enable the hybrid integration of superconductor and semiconductor digital electronics. The design requirements of superconductor-semiconductor interface circuits vary depending on the application, such as high-performance classical computing, superconducting quantum computing, and digital signal processing. In this survey, various interface circuits are categorized based on the working principle and structure. The superconducting output drivers are explored, which are capable of converting and amplifying, e.g., single flux quantum (SFQ) voltage pulses, to voltage levels that semiconductor circuits can process. Several trade-offs between circuit- and system-level design parameters are examined. Accordingly, parameters such as the data rate, output voltage, power dissipation, layout area, thermal/heat load of cryogenic cables, and bit-error rate are considered.Interface circuits are the key components that enable the hybrid integration of superconductor and semiconductor digital electronics. The design requirements of superconductor-semiconductor interface circuits vary depending on the application, such as high-performance classical computing, superconducting quantum computing, and digital signal processing. In this survey, various interface circuits are categorized based on the working principle and structure. The superconducting output drivers are explored, which are capable of converting and amplifying, e.g., single flux quantum (SFQ) voltage pulses, to voltage levels that semiconductor circuits can process. Several trade-offs between circuit- and system-level design parameters are examined. Accordingly, parameters such as the data rate, output voltage, power dissipation, layout area, thermal/heat load of cryogenic cables, and bit-error rate are considered.

physics.app-phCross-listedarXiv:2601.09969Applied Physics ReviewsJan 16, 20260 citations

J_{c}

(4.5 and 20

\hbox{kA/cm}^{2}

) fabrication process.