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IEEE International Conference on Cloud Engineering

A FPGA Based Real-time Design of Efficient Sifting Module in QKD System

Qiong Li, Xiong Shaojin, Dan Le, Zhibin Lin, Liu Hucheng

Published Mar 1, 2014• 1 citation
Publisher

Abstract

Since the Quantum Key Distribution (QKD)technique makes it possible to construct an absolute secure cryptographic system by combing the One-time pad, QKD has drawn many attention these years. The insufficient implementation speed of the post-processing system of QKD is one of the greatest obstacle to wide application of QKD. The sifting module of QKD post-processing system needs to deal with the heaviest incoming load, it is of crucial importance to study how to design and implement an efficient sifting module to accelerate the QKD post-processing system. In this paper, an efficient FPGA based design scheme of the sifting module is presented. Our scheme can decrease the demands for storage resource and communication traffic obviously.

DOI
10.1109/ic2e.2014.22

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Since the Quantum Key Distribution (QKD)technique makes it possible to construct an absolute secure cryptographic system by combing the One-time pad, QKD has drawn many attention these years. The insufficient implementation speed of the post-processing system of QKD is one of the greatest obstacle to wide application of QKD. The sifting module of QKD post-processing system needs to deal with the heaviest incoming load, it is of crucial importance to study how to design and implement an efficient sifting module to accelerate the QKD post-processing system. In this paper, an efficient FPGA based design scheme of the sifting module is presented. Our scheme can decrease the demands for storage resource and communication traffic obviously.
Quantum Key Distribution (QKD) technique has drawn many attentions because it can generate and distribute cryptographic keys with provable information theoretic security. To achieve a high secure key rate, it is a developing trend to adopt the FPGA-based scheme. Sifting is an important processing module of QKD post processing system (QKDPPS) and its communication traffic and input data rate are much larger than other modules of QKDPPS. In this paper, a FPGA-based design of efficient QKD sifting module is presented. To reduce the interaction data amount and thus increase the secure key rate, a high compression ratio round-length based compression encoder and decoder are designed in the sifting modules of two parties. To accelerate the processing speed and thus increase the secure key rate, parallelized processing scheme is designed. The experimental results demonstrate the feasibility and efficiency of the sifting module.
Although the quantum technology introduces an unprecedented threat to the classical encryption field, the combination of Quantum Key Distribution (QKD) and one-time pad makes the absolutely secure encryption possible. However the key distribution rate of most QKD systems still cannot meet the requirements of practical applications. The complex QKD post-processing is one of the largest obstacles to improving the key distribution rate. In this paper, the design and implementation of a multi-thread QKD post-processing software is introduced, including the motivation, architecture and communication protocol. The QKD post processing software is flexible, efficient and easy to implement.
The development of quantum computer technology has brought unprecedented threats to traditional cryptography methods. So far, the combination of Quantum Key Distribution (QKD) and one-time pad cryptography is the best solution to overcome the problem since it makes provable information-theoretic secure encryption possible. While the final key generation rate of most QKD systems cannot meet the needs of practical applications. One of the important reasons is the unsatisfied performance of communication scheme of classical channel in the QKD post processing system (QKDPPS). In this paper, an efficient FPGA-based communication scheme of classical channel in high speed QKD system is presented. Considering the following features of high transmission speed, multiple data types, large data quantity and strict data sequence of the communication over classical channel in a high-speed QKD system, the optical fiber is chosen as the communication medium and a high performance transmission protocol suitable for QKD is designed, including the packeting strategy based on data exchange rate and a reliability assurance scheme on the data link layer. The experimental results demonstrate that our communication scheme can provide stable communication service at 1.66 Gbps for a high-speed QKD system.
Quantum key distribution (QKD), based on quantum mechanics, enables unconditionally secure key exchange even against adversaries with unlimited computing power. As the core of QKD post-processing, information reconciliation (IR) and privacy amplification (PA) ensure key consistency and security by correcting errors and removing leaked information. With the trend toward miniaturized and chip-based QKD systems, post-processing modules require highly integrated designs. FPGAs offer an ideal solution due to their low cost, power efficiency, and flexibility. This paper presents an FPGA-based QKD post-processing architecture using a polar codes-based appending IR algorithm, achieving reconciliation efficiency better than 1.1 under Eµ≥ 0.06 and Rm= 4. A convolution-structured Toeplitz hash module is developed for PA, supporting 53.13 Mbps data rate and 26.45 Mbps key rate with RPA= 0.5. The complete system is implemented on a Xilinx XCKU040 FPGA. Experimental results show support for 176.58 Mbps input, 36.59 Mbps real-time processing, and 17.56 Mbps key output, demonstrating strong performance and engineering suitability. The design features high integration and portability, offering a practical hardware solution for efficient QKD post-processing.
A real-time quantum key distribution (QKD) system is developed in this paper. In the system, based on the feature of a field-programmable gate array, secure key extraction control and algorithm have been optimally designed to perform sifting, error correction, and privacy amplification altogether in real time. In the QKD experiment, information synchronization mechanism and high-speed classic data channel are designed to ensure the steady operation of the system. Decoy state and synchronous laser light source are used in the system, while the length of optical fiber between Alice and Bob is 20 km. With photons repetition frequency of 20 MHz, the final key rate could reach 17 kb/s. Smooth and robust operation is verified with 6 h continuous test and associated with encrypted voice communication test.
In the process of quantum key distribution (QKD), error correction algorithm is used to correct the error bits of the key at both ends. The existing applied QKD system has a low key rate and is generally Kbps of magnitude. Therefore, the performance requirement of data processing such as error correction is not high. In order to cope with the development demand of high-speed QKD system in the future, this paper introduces the Winnow algorithm to realize high-speed parity and hamming error correction based on Field Programmable Gate Array (FPGA), and explores the performance limit of this algorithm. FPGA hardware implementation can achieve the scale of Mbps bandwidth, with choosing different group length of sifted key by different error rate, and can achieve higher error correction efficiency by reducing the information leakage in the process of error correction, and improves the QKD system’s secure key rate, thus helping the future high-speed QKD system.