This paper proposes a VLSI-like design and verification flow for quantum circuit implementation, covering four levels: behavioral modeling, register-transfer level (RTL), gate level, and full-circuit integration with quantum algorithms. Using quantum Monte Carlo methods for pi estimation as a case study, the proposed flow provides a systematic path from initial specifications to large-scale quantum circuit implementation. The paper highlights two key contributions. First, quantum digital design supports a broad range of applications beyond predefined circuit templates. This capability is particularly important for application-specific operations in algorithms such as Shor's, Grover's, and quantum amplitude estimation (QAE), and can significantly advance fault-tolerant quantum computing (FTQC). Second, classical simulation shows that replacing random sampling with grid sampling can achieve a quadratic improvement in this pi-estimation case without quantum computation. This suggests that the quadratic speedup may arise from the grid sampling strategy rather than from the QAE circuit itself. By adapting conventional VLSI digital design principles, this four-level flow addresses a key bottleneck in quantum circuit design and enables flexible design initiation from multiple entry points, including specifications, RTL, and gate-level descriptions, paving the way for the practical deployment of quantum computing.
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The paper asks how conventional VLSI design and verification practices can be adapted to quantum circuits, particularly for application-specific operations that are not supplied by predefined circuit templates. It proposes a four-level workflow spanning behavioral modeling, register-transfer level (RTL), gate-level design, and integration into a complete quantum algorithm. Quantum Monte Carlo estimation of $\pi$ serves as the case study. The workflow is intended to support entry from specifications, RTL descriptions, or gate-level descriptions, with applications envisaged in Shor’s algorithm, Grover search, and quantum amplitude estimation (QAE).
The abstract reports that classical simulations of this estimation task obtain a quadratic improvement by replacing random sampling with grid sampling, without quantum computation. It interprets this as suggesting that the apparent quadratic advantage in this example may originate from the sampling strategy rather than QAE itself. This is a case-specific claim: the abstract does not specify the error metric, sampling-cost model, or asymptotic bounds needed to compare it with standard QAE guarantees.
Only the title and abstract are available. They do not provide circuit sizes, resource estimates, verification procedures, simulation parameters, or quantitative comparisons with existing design workflows. No explicit limitations are stated in the abstract, so the demonstrated implementation scale and the scope of the sampling comparison cannot be assessed from the available material.
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This paper proposes a VLSI-like design and verification flow for quantum circuit implementation, covering four levels: behavioral modeling, register-transfer level (RTL), gate level, and full-circuit integration with quantum algorithms. Using quantum Monte Carlo methods for pi estimation as a case study, the proposed flow provides a systematic path from initial specifications to large-scale quantum circuit implementation. The paper highlights two key contributions. First, quantum digital design supports a broad range of applications beyond predefined circuit templates. This capability is particularly important for application-specific operations in algorithms such as Shor's, Grover's, and quantum amplitude estimation (QAE), and can significantly advance fault-tolerant quantum computing (FTQC). Second, classical simulation shows that replacing random sampling with grid sampling can achieve a quadratic improvement in this pi-estimation case without quantum computation. This suggests that the quadratic speedup may arise from the grid sampling strategy rather than from the QAE circuit itself. By adapting conventional VLSI digital design principles, this four-level flow addresses a key bottleneck in quantum circuit design and enables flexible design initiation from multiple entry points, including specifications, RTL, and gate-level descriptions, paving the way for the practical deployment of quantum computing.
The paper asks how conventional VLSI design and verification practices can be adapted to quantum circuits, particularly for application-specific operations that are not supplied by predefined circuit templates. It proposes a four-level workflow spanning behavioral modeling, register-transfer level (RTL), gate-level design, and integration into a complete quantum algorithm. Quantum Monte Carlo estimation of π serves as the case study. The workflow is intended to support entry from specifications, RTL descriptions, or gate-level descriptions, with applications envisaged in Shor’s algorithm, Grover search, and quantum amplitude estimation (QAE).
The abstract reports that classical simulations of this estimation task obtain a quadratic improvement by replacing random sampling with grid sampling, without quantum computation. It interprets this as suggesting that the apparent quadratic advantage in this example may originate from the sampling strategy rather than QAE itself. This is a case-specific claim: the abstract does not specify the error metric, sampling-cost model, or asymptotic bounds needed to compare it with standard QAE guarantees.
Only the title and abstract are available. They do not provide circuit sizes, resource estimates, verification procedures, simulation parameters, or quantitative comparisons with existing design workflows. No explicit limitations are stated in the abstract, so the demonstrated implementation scale and the scope of the sampling comparison cannot be assessed from the available material.
In this work, we introduce “Quantum-Chiplet”, a novel design flow for quantum circuits via a VLSI-like methodology. A large-scale quantum problem is hierarchically decomposed into several functions, or “chiplets,” and designed one by one. Each “chiplet” is initially represented with a behavior model without the need for quantum gate-level details, allowing for greater flexibility in designing arbitrary digital logic under any qubit count within a quantum environment. Focusing on behavior-level design, we also shorten the simulation time by more than an order of magnitude, as demonstrated by comparing the simulation time of QuantumChiplet to the conventional quantum simulator, Qiskit. To synthesize the design into real quantum gates, we leverage the conventional VLSI tool–Design Compiler for the automatic generation of quantum-gate-level design and automatically translate it into code interpretable by conventional quantum simulators. Moreover, Quantum-Chiplet utilizes matrices and the Python NumPy library for simulation. So even if suitable quantum gates are hard to find in existing libraries, simulations can still be done. These advancements, from bottom to top, pave the way for efficiently simulating and scaling up quantum circuits, and offer insight into electronic design automation for next-generation fault-tolerant quantum computing.
This research paper provides an in-depth examination of verification and testing approaches for quantum circuits, focusing on methodologies essential for ensuring the correctness, reliability and operational efficiency of quantum computing systems. Since quantum circuits function on the fundamental principles of superposition and entanglement, they present verification challenges that cannot be effectively addressed using conventional classical testing techniques. As a result, the development of specialized quantum-specific verification strategies has become critically important. The study highlights simulation-based verification as a foundational technique, wherein the outcomes of quantum circuit simulations are systematically compared with results obtained from physical quantum hardware. This process enables the identification of functional inconsistencies and supports iterative refinement of circuit designs. In addition, randomized benchmarking is examined as a key evaluation method for estimating circuit fidelity and quantifying error rates through the application of random gate sequences and performance comparisons against established benchmarks. To further improve system robustness, the research investigates fault-tolerant mechanisms, particularly quantum error correction codes, which play a vital role in minimizing the effects of noise, decoherence and hardware imperfections. The integration of advanced quantum metrology and characterization techniques is also explored, enabling precise measurement and detailed analysis of quantum system behavior. These techniques provide deeper insights into circuit performance and contribute significantly to validation processes. By combining simulation-based verification, randomized benchmarking, fault-tolerant protocols and quantum metrology, this study proposes a comprehensive and reliable framework for quantum circuit verification and testing. The findings contribute to the advancement of dependable quantum technologies and support their growing applications in areas such as cryptography, materials science and other emerging domains.
Monte Carlo methods are fundamental to finance, system verification, and scientific simulation, but converge slowly: achieving an additive error of є requires O (1/є 2 ) samples. Quantum Amplitude Estimation (QAE) offers a quadratic speedup by encoding the target probabilistic model into a quantum circuit. However, constructing such a circuit demands low-level quantum expertise, and existing tools for this task all sacrifice at least one of generality, usability, or efficiency. To address these, we design QPPL (Quantum Probabilistic Programming Language), a simple imperative language, and a compiler that translates probabilistic programs into quantum circuits. The key insight is that the circuit construction amounts to specifying a probability distribution, precisely the task that probabilistic programming addresses. QPPL achieves generality by supporting joint distributions, conditional updates, dynamic probabilities, and real-valued expectations in a single language; usability by offering a sequential, imperative syntax with named variables and direct arithmetic that hides all quantum details; and efficiency by modularly compiling each construct into reversible circuit primitives, achieving scalable circuit synthesis. We prove that the compilation is semantics-preserving. On benchmarks spanning finance and probabilistic model checking, QPPL is the only tool that covers all benchmarks, while producing circuits with up to 8.8× fewer gates and 26× shallower depth than existing tools.
This study presents a quantum circuit for estimating the pi value using arithmetic circuits and by quantum amplitude estimation. We review two types of quantum multipliers and propose quantum squaring circuits based on the multiplier as basic arithmetic circuits required for performing quantum computations. The squarer realized by a quantum adder with the gate size of $ O(n) $ requires $ O(n^2) $ gates and at least one ancillary qubits, while that realized by using quantum Fourier transform (QFT) requires $ O(n^3) $ gates without ancillary qubit. The proposed quantum circuit to estimate pi is based on the Monte Carlo method, quantum amplitude estimation, and quantum squarer. By applying the quantum squarer using QFT, the circuit was implemented in $ 4n + 1 $ qubits at $ 2^{2n} $ sampling. The proposed method was demonstrated using a quantum computer simulator with $ n $ being varied from 2 to 6, and the obtained result was compared with the one obtained by performing a classical calculation.
The rapid advancement of Noisy Intermediate-Scale Quantum (NISQ) devices has driven the need for efficient design automation tools that can translate complex engineering models into executable quantum circuits. This study explores the development of automated quantum circuit design frameworks focused on gate optimization and noise-aware compilation, enabling practical quantum computation for engineering applications such as optimization, simulation, and control systems. Traditional circuit design methods often fail to account for hardware constraints, decoherence, and gate infidelity, which significantly affect computational accuracy on NISQ devices. To address these challenges, this research introduces a hybrid automation approach combining quantum transpilation, variational circuit pruning, and error-aware synthesis algorithms to enhance circuit reliability and scalability. The framework integrates quantum-classical co-design principles to optimize both logical and physical circuit layers, leveraging hardware-specific calibration data to adapt compilation strategies dynamically. Through simulations and benchmark analysis, the proposed system demonstrates significant improvements in quantum resource utilization, error mitigation, and gate depth reduction compared to conventional compilation methods. This work underscores the growing importance of design automation in quantum engineering, where algorithmic efficiency must be harmonized with physical constraints to realize functional and scalable quantum workflows. By establishing a methodology for gate-level optimization and noise-adaptive design, the study contributes to bridging the gap between theoretical quantum algorithms and real-world engineering implementations within the NISQ computing era.
Prior studies have largely focused on quantum algorithms, often reducing parallel computing designs to abstract models or overly simplified circuits. This has contributed to the misconception that most applications are feasible only through VLSI circuits and cannot be implemented using quantum circuits. To challenge this view, we present a mixed-signal quantum circuit framework incorporating three novel methods that reduce circuit complexity and improve noise tolerance. In a 12 qubit case study comparing our design with JP Morgan's option pricing circuit, we reduced the gate count from 4095 to 392, depth from 2048 to 6, and error rate from 25.86\% to 1.64\%. Our design combines analog simplicity with digital flexibility and synthesizability, demonstrating that quantum circuits can effectively leverage classical VLSI techniques, such as those enabled by Synopsys Design Compiler to address current quantum design limitations.