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arXiv:2008.02623

Quantum circuit to estimate pi using quantum amplitude estimation

Takuma Noto

Published Aug 4, 2020• 2 citations
arXivHTMLPDF

Abstract

This study presents a quantum circuit for estimating the pi value using arithmetic circuits and by quantum amplitude estimation. We review two types of quantum multipliers and propose quantum squaring circuits based on the multiplier as basic arithmetic circuits required for performing quantum computations. The squarer realized by a quantum adder with the gate size of $ O(n) $ requires $ O(n^2) $ gates and at least one ancillary qubits, while that realized by using quantum Fourier transform (QFT) requires $ O(n^3) $ gates without ancillary qubit. The proposed quantum circuit to estimate pi is based on the Monte Carlo method, quantum amplitude estimation, and quantum squarer. By applying the quantum squarer using QFT, the circuit was implemented in $ 4n + 1 $ qubits at $ 2^{2n} $ sampling. The proposed method was demonstrated using a quantum computer simulator with $ n $ being varied from 2 to 6, and the obtained result was compared with the one obtained by performing a classical calculation.

DOI
10.48550/arxiv.2008.02623

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Quantum circuits which perform integer arithmetic could potentially outperform their classical counterparts. In this paper, a quantum circuit is considered which performs a specific computational pattern on classically represented integers to accelerate the computation. Such a hybrid circuit could be embedded in a conventional computer architecture as a quantum device or accelerator. In particular, a quantum multiply-add circuit (QMAC) using a Quantum Fourier Transform (QFT) is proposed which can perform the calculation on conventional integers faster than its conventional counterpart. Whereas classically applying a multiply-adder (MAC) nnn times to kkk bit integers would require O(nlog⁡k)O(n \log k)O(nlogk) parallel steps, the hybrid QMAC needs only O(n+k)O(n + k)O(n+k) steps for the exact result and O(n+log⁡k)O(n + \log k)O(n+logk) steps for an approximate result.
This paper proposes a VLSI-like design and verification flow for quantum circuit implementation, covering four levels: behavioral modeling, register-transfer level (RTL), gate level, and full-circuit integration with quantum algorithms. Using quantum Monte Carlo methods for pi estimation as a case study, the proposed flow provides a systematic path from initial specifications to large-scale quantum circuit implementation. The paper highlights two key contributions. First, quantum digital design supports a broad range of applications beyond predefined circuit templates. This capability is particularly important for application-specific operations in algorithms such as Shor's, Grover's, and quantum amplitude estimation (QAE), and can significantly advance fault-tolerant quantum computing (FTQC). Second, classical simulation shows that replacing random sampling with grid sampling can achieve a quadratic improvement in this pi-estimation case without quantum computation. This suggests that the quadratic speedup may arise from the grid sampling strategy rather than from the QAE circuit itself. By adapting conventional VLSI digital design principles, this four-level flow addresses a key bottleneck in quantum circuit design and enables flexible design initiation from multiple entry points, including specifications, RTL, and gate-level descriptions, paving the way for the practical deployment of quantum computing.
A quantum gate is the quantum analog of the classical logic gate of digital computers. It is a basic structural unit of a quantum circuit which operates on a small number of qubits to deliver a predefined output. A quantum circuit is a graphical representation of the sequence of the quantum gates used and the measurements performed in a quantum computation. Various quantum logic gates, namely, the Hadamard, T phase, NOT, Pauli-X, controlled NOT (CNOT), controlled-Z, SWAP and controlled phase gates as well as higher-level Toffoli and Fredkin gates are described. Conventions of reading quantum circuit diagrams are explained. Operation of a quantum full adder consisting of registers and gates is discussed, elaborating the role of the NOT gate, the sum calculation with CNOTgates and the carry C-out calculation with Toffoli gates. A primary tool used for performing arithmetic operations on a quantum computer is the quantum Fourier transform (QFT). The QFT adder and multiplier circuits are presented.
Quantum squaring circuits have been used as helpful arithmetic modules in various quantum algorithms for calculating series expansions or distances of vectors, etc. Quantum multipliers can replace quantum squaring circuits, but squaring with quantum multipliers is inefficient because it involves using quantum gates for unnecessary bitwise multiplication. In this paper, we propose a depth-optimized quantum circuit dedicated to squaring by eliminating these unnecessary quantum gates and implementing quantum gates in parallel. We also discuss the optimal distribution of the partial products to reduce further the gate cost of the quantum adder used for the sum of the partial products. The proposed partial product distribution method lowers the quantum adder’s number of gates and depth by half. Our quantum squaring circuit is the most efficient, with an average improvement of 68% and 79.7% in T-count and T-depth, respectively, compared to existing quantum squaring circuits. Despite the increased qubit counts caused by the depth optimization, we demonstrate that the proposed circuit has the smallest KQT\hbox {KQ}_\textrm{T}KQT​ .
In this research, we create a scalable version of the quantum Fourier transform-based arithmetic circuit to perform addition and subtraction operations on N n-bit unsigned integers encoded in quantum registers, and it is compatible with d-level quantum sources, called qudits. We present qubit- and ququart-based multi-input QFT adders, and we compare and discuss potential benefits such as circuit simplicity and noise sensitivity. The results show that a ququart-based system significantly reduces gate count and improves computational efficiency compared to qubit-based systems. Overall, the findings presented in this study represent a promising step forward in the development of efficient quantum arithmetic circuits, particularly for multi-input operations, with clear advantages for ququart-based systems in reducing gate count, decoherence, and circuit complexity.