Prior studies have largely focused on quantum algorithms, often reducing parallel computing designs to abstract models or overly simplified circuits. This has contributed to the misconception that most applications are feasible only through VLSI circuits and cannot be implemented using quantum circuits. To challenge this view, we present a mixed-signal quantum circuit framework incorporating three novel methods that reduce circuit complexity and improve noise tolerance. In a 12 qubit case study comparing our design with JP Morgan's option pricing circuit, we reduced the gate count from 4095 to 392, depth from 2048 to 6, and error rate from 25.86\% to 1.64\%. Our design combines analog simplicity with digital flexibility and synthesizability, demonstrating that quantum circuits can effectively leverage classical VLSI techniques, such as those enabled by Synopsys Design Compiler to address current quantum design limitations.
Prior studies have largely focused on quantum algorithms, often reducing parallel computing designs to abstract models or overly simplified circuits. This has contributed to the misconception that most applications are feasible only through VLSI circuits and cannot be implemented using quantum circuits. To challenge this view, we present a mixed-signal quantum circuit framework incorporating three novel methods that reduce circuit complexity and improve noise tolerance. In a 12 qubit case study comparing our design with JP Morgan's option pricing circuit, we reduced the gate count from 4095 to 392, depth from 2048 to 6, and error rate from 25.86% to 1.64%. Our design combines analog simplicity with digital flexibility and synthesizability, demonstrating that quantum circuits can effectively leverage classical VLSI techniques, such as those enabled by Synopsys Design Compiler to address current quantum design limitations.
Large-scale quantum computers that can execute practical quantum algorithms have the potential to solve complex problems that are currently challenging for classical computers. This involves converting these problems into a form that can be processed by quantum circuits, a crucial process that requires minimizing quantum resources like qubit count, gate count, and circuit depth. Our work focuses on implementing and optimizing the foundational task of quantum finance, known as option pricing, as a quantum circuit. This enables the utilization of quantum computing benefits, within the financial domain. Specifically, we implement and optimize the function fK(S) = max(S−K, 0). Taking into consideration the significant trade-offs between qubit count and circuit depth, we have developed quantum circuits for the optimized implementation of the fK(S). Our work incorporates various optimization techniques for the circuit, such as selecting the optimal adder, optimizing the S−K operation, parallelization, and qubit reuse. Furthermore, we offer various versions of our quantum circuits for the fK(S), each featuring different adders and Toffoli decompositions, thereby providing flexibility for a wide range of use cases.
The rapid advancement of Noisy Intermediate-Scale Quantum (NISQ) devices has driven the need for efficient design automation tools that can translate complex engineering models into executable quantum circuits. This study explores the development of automated quantum circuit design frameworks focused on gate optimization and noise-aware compilation, enabling practical quantum computation for engineering applications such as optimization, simulation, and control systems. Traditional circuit design methods often fail to account for hardware constraints, decoherence, and gate infidelity, which significantly affect computational accuracy on NISQ devices. To address these challenges, this research introduces a hybrid automation approach combining quantum transpilation, variational circuit pruning, and error-aware synthesis algorithms to enhance circuit reliability and scalability. The framework integrates quantum-classical co-design principles to optimize both logical and physical circuit layers, leveraging hardware-specific calibration data to adapt compilation strategies dynamically. Through simulations and benchmark analysis, the proposed system demonstrates significant improvements in quantum resource utilization, error mitigation, and gate depth reduction compared to conventional compilation methods. This work underscores the growing importance of design automation in quantum engineering, where algorithmic efficiency must be harmonized with physical constraints to realize functional and scalable quantum workflows. By establishing a methodology for gate-level optimization and noise-adaptive design, the study contributes to bridging the gap between theoretical quantum algorithms and real-world engineering implementations within the NISQ computing era.
We present a methodology to price options and portfolios of options on a gate-based quantum computer using amplitude estimation, an algorithm which provides a quadratic speedup compared to classical Monte Carlo methods. The options that we cover include vanilla options, multi-asset options and path-dependent options such as barrier options. We put an emphasis on the implementation of the quantum circuits required to build the input states and operators needed by amplitude estimation to price the different option types. Additionally, we show simulation results to highlight how the circuits that we implement price the different option contracts. Finally, we examine the performance of option pricing circuits on quantum hardware using the IBM Q Tokyo quantum device. We employ a simple, yet effective, error mitigation scheme that allows us to significantly reduce the errors arising from noisy two-qubit gates.
The growing complexity of Very Large Scale Integration (VLSI) circuit designs has significantly increased the demand for innovative approaches to enhance design efficiency and fabrication accuracy. Traditional computational methods face limitations in terms of scalability and optimization for complex VLSI systems. The advent of quantum computing presents a promising paradigm shift, offering exponential speedup in solving computationally intensive problems such as optimization, simulation, and data analysis in VLSI design and fabrication. This research investigates the potential of quantum computing algorithms to optimize VLSI circuit design and fabrication processes, addressing key challenges such as layout optimization, routing, and process variation. The problem lies in the increasing complexity and size of VLSI circuits, which often lead to inefficient designs, longer manufacturing times, and increased cost. Current methods such as classical algorithms and heuristic techniques struggle to achieve optimal solutions within reasonable time frames. Quantum algorithms, particularly those based on quantum annealing and variational quantum eigensolvers (VQE), have shown promise in solving combinatorial optimization problems with much higher efficiency. By leveraging quantum computing, the goal is to improve the optimization of circuit layouts, minimize power consumption, and reduce production costs in VLSI systems. The proposed method utilizes quantum computing techniques to model and solve optimization problems related to VLSI circuit design and fabrication. Simulations and comparisons with classical methods show significant improvements in design efficiency, reduced error rates, and faster optimization cycles. The outcomes of this study could transform the future of VLSI design and fabrication, leading to more efficient, cost-effective, and scalable solutions for semiconductor manufacturing.
This paper proposes a VLSI-like design and verification flow for quantum circuit implementation, covering four levels: behavioral modeling, register-transfer level (RTL), gate level, and full-circuit integration with quantum algorithms. Using quantum Monte Carlo methods for pi estimation as a case study, the proposed flow provides a systematic path from initial specifications to large-scale quantum circuit implementation. The paper highlights two key contributions. First, quantum digital design supports a broad range of applications beyond predefined circuit templates. This capability is particularly important for application-specific operations in algorithms such as Shor's, Grover's, and quantum amplitude estimation (QAE), and can significantly advance fault-tolerant quantum computing (FTQC). Second, classical simulation shows that replacing random sampling with grid sampling can achieve a quadratic improvement in this pi-estimation case without quantum computation. This suggests that the quadratic speedup may arise from the grid sampling strategy rather than from the QAE circuit itself. By adapting conventional VLSI digital design principles, this four-level flow addresses a key bottleneck in quantum circuit design and enables flexible design initiation from multiple entry points, including specifications, RTL, and gate-level descriptions, paving the way for the practical deployment of quantum computing.
Variational quantum algorithms (VQAs) hold significant promise for solving complex problems across diverse fields. However, their practical implementation on near-term quantum devices is severely hampered by the pervasive effects of quantum noise. Traditional quantum circuit compilation techniques are largely static, failing to account for the unique noise profiles inherent in individual quantum hardware. This paper introduces a novel adaptive quantum circuit compilation framework designed to mitigate these limitations. The core concept centers around dynamically adjusting the circuit layout and gate decomposition in real-time, leveraging measurements of the quantum hardware's noise characteristics to optimize both the accuracy and circuit depth of the compiled quantum circuit. This approach represents a critical step towards unlocking the full potential of VQAs by enabling them to effectively operate within the constraints of noisy quantum computers. The framework incorporates feedback loops for continuous refinement, adapting to evolving noise conditions. The methodology is described, focusing on the key components: noise profiling, adaptive gate decomposition, and circuit re-optimization. Simulation results demonstrate the effectiveness of the adaptive approach in reducing circuit depth and improving the fidelity of VQA computations compared to static compilation methods. This work lays the foundation for robust and efficient VQA execution on future quantum hardware.