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arXiv:2607.16166

Fast logical operations in quantum LDPC codes using simple resource states

Mark Webster, Nicolas Delfosse

quant-phSubmitted Jul 17, 2026• Announced Jul 20, 2026• 0 citations
v1 · Jul 17, 2026v2 · Jul 30, 2026
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Abstract

Quantum LPDC codes provide a substantial reduction in qubit overhead required for fault-tolerant quantum computation compared to surface code, thanks to their high encoding rate. However, operating simultaneously on multiple logical qubits encoded in the same block is more challenging and may slow down logical operations. Prior work addresses this problem by designing complex resource states to perform logical measurements in LDPC codes. Here, we propose an approach that only consumes cat states. Whereas previous work on cat-based measurements focuses on a single logical measurement, we design a protocol for the joint measurement of $\ell$ commuting logical operators. The key ingredient is the design of a scheduler code determining the measurement sequence and allowing for the decoding of all logical measurement outcomes. Numerical simulations with the LDPC codes Q70 and Q102 of the walking cat architecture show a speed-up of nearly $3\times$ over Viterbi measurements for the measurement of $\ell=20$ commuting logical operators. Combining our fast logical measurements with a new variant of the CliNR partial error correction scheme, we achieve a speed up of up to up to $74\times$ for random Clifford circuits. Our approach also applies to non-Clifford gates, producing a speed up of up to $5\times$ for Toffoli gates.

Comments
14 pages, 4 figure

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Quantum LPDC codes provide a substantial reduction in qubit overhead required for fault-tolerant quantum computation compared to surface code, thanks to their high encoding rate. However, operating simultaneously on multiple logical qubits encoded in the same block is more challenging and may slow down logical operations. Prior work addresses this problem by designing complex resource states to perform logical measurements in LDPC codes. Here, we propose an approach that only consumes cat states. Whereas previous work on cat-based measurements focuses on a single logical measurement, we design a protocol for the joint measurement of ℓ\ellℓ commuting logical operators. The key ingredient is the design of a scheduler code determining the measurement sequence and allowing for the decoding of all logical measurement outcomes. Numerical simulations with the LDPC codes Q70 and Q102 of the walking cat architecture show a speed-up of nearly 3×3\times3× over Viterbi measurements for the measurement of ℓ=20\ell=20ℓ=20 commuting logical operators. Combining our fast logical measurements with a new variant of the CliNR partial error correction scheme, we achieve a speed up of up to up to 74×74\times74× for random Clifford circuits. Our approach also applies to non-Clifford gates, producing a speed up of up to 5×5\times5× for Toffoli gates.
Quantum computing relies on quantum error correction for high-fidelity logical operations, but scaling to achieve near-term quantum utility is highly resource-intensive. High-rate quantum LDPC codes can reduce error correction overhead, yet realizing high-rate fault-tolerant computation with these codes remains a central challenge. Apart of the lattice surgery approach, standard schemes for realizing logical gates have so far been restricted to performing global operations on all logical qubits at the same time. Another approach relies on low-rate code switching methods. In this work, we introduce a gate-based protocol for addressable single- and multi-qubit Clifford operations on individual logical qubits encoded within one or more quantum LDPC codes. Our scheme leverages logical transversal operations via an auxiliary Bacon-Shor code to perform logical operations with constant time overhead enabled by teleportation. We demonstrate the implementation of an overcomplete logical Clifford gate set and perform numerical simulations to evaluate the error-correction performance of our protocol. Finally, we observe that our scheme can be integrated with magic state cultivation protocols to achieve universal, gate-based, and fully addressable quantum computation.
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We propose a fault-tolerant quantum computer architecture for trapped-ion devices, which we call the walking cat architecture. Our blueprint includes a compiler, a detailed description of all the quantum error-correction protocols, a micro-architecture, a sufficiently fast decoder, and thorough simulations. The backbone of the architecture is a cat factory, producing cat states distributed throughout the machine, which are consumed to perform logical operations. The walking cat architecture is based entirely on a modern quantum error-correction approach called low-density parity-check (LDPC) codes. We identify promising instances of the walking cat architecture, such as (1) a simple architecture based on a single LDPC code, (2) a fast architecture based on fast logical gates relying on a [[70, 6, 9]] code, equipped with Clifford-frame tracking for any 6-qubit Clifford gate, and (3) a dense architecture based on a [[102, 22, 9]]] code encoding 22 logical qubits per memory block. Our dense architecture provides a design with 110 logical qubits executing about one million T gates per day using only 2,514 physical qubits. We estimate that the quantum Hamiltonian simulation of a Heisenberg model on 100 sites can be executed within one month with 10,000 physical qubits, including all shots required to achieve chemical accuracy, suggesting that such a device could enter the regime of classically intractable physics simulations. Our design relies on hardware components that have been experimentally demonstrated on small devices. We emphasize simplicity over hypothetical performance to facilitate the practical realization of this machine. Based on this approach, we believe that a fault-tolerant quantum computer with hundreds of logical qubits capable of running millions of logical gates can be built in the near term, providing a platform to explore a broad range of applications.
High-rate quantum LDPC (qLDPC) codes reduce memory overhead by densely packing many logical qubits into a single block of physical qubits. Here we extend this concept to high-rate computation by constructing \emph{batched} fault-tolerant operations that apply the same logical gate across many code blocks in parallel. By leveraging shared physical resources to execute many logical operations in parallel, these operations realize high rates in space-time and significantly reduce computational costs. For \emph{arbitrary} CSS qLDPC codes, we build batched gadgets with \emph{constant space-time overhead} (assuming fast classical computation) for (i) single-shot error correction, state preparation, and code surgeries (ii) code switching, and (iii) addressable Clifford gates. Using these batched gadgets we also construct parallel non-Clifford gates with low space-time cost. We outline principles for designing parallel quantum algorithms optimized for a batched architecture, and show in particular how lattice Hamiltonian dynamical simulations can be compiled efficiently. We also propose a near-term implementation using new self-dual Bivariate-Bicycle codes with high encoding rates (∼1/10\sim 1/10∼1/10), transversal Clifford gates, and global TTT gates via parallel magic state cultivation, enabling Hamiltonian simulations with a lower space-time cost than analogous surface-code protocols and low-rate qLDPC protocols. These results open new paths toward scalable quantum computation via co-design of parallel quantum algorithms and high-rate fault-tolerant protocols.
Quantum low-density parity-check (qLDPC) codes can substantially reduce the qubit overhead of fault-tolerant quantum computation, but any useful architecture based on such codes also requires an efficient mechanism to implement non-Clifford gates in a fault-tolerant manner. We introduce a space-time-efficient magic state factory for high-rate qLDPC codes by combining the transversal non-Clifford gates of recently developed tricycle codes with single-shot four-dimensional balanced product quadcycle codes. The key ingredient is an efficient "escape" mechanism that teleports postselected logical magic states from tricycle codes to larger distance quadcycle codes. Under a standard circuit-level noise model at physical error rate 10−310^{-3}10−3, our factories produce CCZ\mathrm{CCZ}CCZ states at logical error rates as low as 10−910^{-9}10−9 with 10-40 times lower space-time cost than state-of-the-art magic state generation methods. The resulting states are directly encoded in high-rate blocks suitable for computation. We identify the quadcycle codes by an AI-assisted search and show that they can serve as excellent memories capable of single-shot error correction. Finally, we present a concrete implementation of the entire factory with highly efficient atom transport on reconfigurable neutral-atom quantum computers. Together, these results provide an end-to-end, practical protocol for producing and utilizing high-fidelity magic states within a high-rate qLDPC architecture, with the lowest space-time cost to date.
One of the most promising routes towards fault-tolerant quantum computation utilizes topological quantum error correcting codes, such as the Z2{\mathbb{Z}}_{2}Z2​ surface code. Logical qubits can be encoded in a variety of ways in the surface code, based on either boundary defects, holes, or bulk twist defects. However, proposed fault-tolerant implementations of the Clifford group in these schemes are limited and often require unnecessary overhead. For example, the Clifford phase gate in certain planar and hole encodings has been proposed to be implemented using costly state injection and distillation protocols. In this paper, we show that within any encoding scheme for the logical qubits, we can fault tolerantly implement the full Clifford group by using joint measurements involving a single appropriately encoded logical ancilla. This allows us to provide low overhead implementations of the full Clifford group in surface and color codes. It also provides the first proposed implementations of the full Clifford group in hyperbolic codes. We further use our methods to propose state-of-the art encoding schemes for small numbers of logical qubits; for example, for code distances d=3,5,7d=3,5,7d=3,5,7, we propose a scheme using 60,160,30860,160,30860,160,308 (respectively) physical data qubits, which allow for the full logical Clifford group to be implemented on two logical qubits. To our knowledge, this is the optimal proposal to date, and thus may be useful for demonstration of fault-tolerant logical gates in small near-term quantum computers.