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arXiv:2511.06124

Addressable gate-based logical computation with quantum LDPC codes

Laura Pecorari, Francesco Paolo Guerci, Hugo Perrin, Guido Pupillo

quant-phSubmitted Nov 8, 2025• Announced Nov 11, 2025• 0 citations
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Abstract

Quantum computing relies on quantum error correction for high-fidelity logical operations, but scaling to achieve near-term quantum utility is highly resource-intensive. High-rate quantum LDPC codes can reduce error correction overhead, yet realizing high-rate fault-tolerant computation with these codes remains a central challenge. Apart of the lattice surgery approach, standard schemes for realizing logical gates have so far been restricted to performing global operations on all logical qubits at the same time. Another approach relies on low-rate code switching methods. In this work, we introduce a gate-based protocol for addressable single- and multi-qubit Clifford operations on individual logical qubits encoded within one or more quantum LDPC codes. Our scheme leverages logical transversal operations via an auxiliary Bacon-Shor code to perform logical operations with constant time overhead enabled by teleportation. We demonstrate the implementation of an overcomplete logical Clifford gate set and perform numerical simulations to evaluate the error-correction performance of our protocol. Finally, we observe that our scheme can be integrated with magic state cultivation protocols to achieve universal, gate-based, and fully addressable quantum computation.

Comments
12 pages, 3 figures

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Quantum computing relies on quantum error correction for high-fidelity logical operations, but scaling to achieve near-term quantum utility is highly resource-intensive. High-rate quantum LDPC codes can reduce error correction overhead, yet realizing high-rate fault-tolerant computation with these codes remains a central challenge. Apart of the lattice surgery approach, standard schemes for realizing logical gates have so far been restricted to performing global operations on all logical qubits at the same time. Another approach relies on low-rate code switching methods. In this work, we introduce a gate-based protocol for addressable single- and multi-qubit Clifford operations on individual logical qubits encoded within one or more quantum LDPC codes. Our scheme leverages logical transversal operations via an auxiliary Bacon-Shor code to perform logical operations with constant time overhead enabled by teleportation. We demonstrate the implementation of an overcomplete logical Clifford gate set and perform numerical simulations to evaluate the error-correction performance of our protocol. Finally, we observe that our scheme can be integrated with magic state cultivation protocols to achieve universal, gate-based, and fully addressable quantum computation.
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Quantum error correction is essential for building utility-scale quantum computers that outperform classical machines, yet leading approaches incur substantial physical qubit overhead. Quantum low-density parity check (QLDPC) codes offer a promising alternative by significantly reducing the number of physical qubits required per logical qubit. However, existing work on QLDPC codes has focused primarily on quantum memories, with no efficient method known for implementing arbitrary logical Clifford operations at low circuit depth. Here, we introduce a new family of QLDPC codes that enables efficient implementation of the full Clifford group via transversal operations, allowing any m-qubit Clifford operation to be executed in at most O(m) syndrome extraction rounds. We run circuit-level simulations of depth-126 logical circuits to demonstrate the near-memory logical performance of these logical operations. In combination with known methods for implementing T gates, these results establish QLDPC codes as a viable route toward resource-efficient universal quantum computation. Quantum LDPC codes can shield quantum computers from decoherence with minimal overhead. In this work, the authors describe a new QLDPC family, SHYPS, as a path to practical fault tolerance with efficient Clifford circuit implementation on encoded states.
Quantum LPDC codes provide a substantial reduction in qubit overhead required for fault-tolerant quantum computation compared to surface code, thanks to their high encoding rate. However, operating simultaneously on multiple logical qubits encoded in the same block is more challenging and may slow down logical operations. Prior work addresses this problem by designing complex resource states to perform logical measurements in LDPC codes. Here, we propose an approach that only consumes cat states. Whereas previous work on cat-based measurements focuses on a single logical measurement, we design a protocol for the joint measurement of ℓ\ellℓ commuting logical operators. The key ingredient is the design of a scheduler code determining the measurement sequence and allowing for the decoding of all logical measurement outcomes. Numerical simulations with the LDPC codes Q70 and Q102 of the walking cat architecture show a speed-up of nearly 3×3\times3× over Viterbi measurements for the measurement of ℓ=20\ell=20ℓ=20 commuting logical operators. Combining our fast logical measurements with a new variant of the CliNR partial error correction scheme, we achieve a speed-up of up to 74×74\times74× for random Clifford circuits. Our approach also applies to non-Clifford gates, producing a speed-up of up to 5×5\times5× for Toffoli gates.
We show that universal quantum computation can be concretely made fault-tolerant without mid-circuit measurements. To this end, we introduce a measurement-free deformation protocol of the Bacon-Shor code to realize a logical gate. Combined with a fold-transversal logical Hadamard gate, this enables a universal set of fault-tolerant operations using only transversal gates and qubit permutations. For the purpose of benchmarking under circuit-level noise, we develop an efficient method to simulate non-Clifford circuits with a small number of Hadamard gates. Separately, we demonstrate that certain CSS codes can be concatenated without measurements or having to rely on a universal logical gate set. This is made possible by means of a resource-efficient gadget—termed the “disposable Toffoli gadget”—that realizes the error-correcting feedback. Then, under concatenation of the Bacon-Shor code, we observe a fault-tolerance threshold at a circuit-level depolarizing noise rate of approximately 0.12 % . Together, the deformation and concatenation protocols outline a blueprint for a fully fault-tolerant architecture without any feed-forward operation, particularly suited to state-of-the-art neutral-atom platforms.