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arXiv:2511.10191

Addressable fault-tolerant universal quantum gate operations for high-rate lift-connected surface codes

Josias Old, Juval Bechar, Markus Müller, Sascha Heußen

quant-phSubmitted Nov 13, 2025• Announced Nov 14, 2025• 0 citations
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Abstract

Quantum low-density parity check (qLDPC) codes are among the leading candidates to realize error-corrected quantum memories with low qubit overhead. Potentially high encoding rates and large distance relative to their block size make them appealing for practical suppression of noise in near-term quantum computers. In addition to increased qubit-connectivity requirements compared to more conventional topological quantum error correcting codes, qLDPC codes remain notoriously hard to compute with. In this work, we introduce a construction to implement all Clifford quantum gate operations on the recently introduced lift-connected surface (LCS) codes (Old et al. 2024). These codes can be implemented in a 3D-local architecture and achieve asymptotic scaling $[[n, \mathcal{O}(n^{1/3}), \mathcal{O}(n^{1/3})]]$. In particular, LCS codes realize favorable instances with small numbers of qubits: For the $[[15,3,3]]$ LCS code, we provide deterministic fault-tolerant (FT) circuits of the logical gate set $\{\overline{H}_i, \overline{H}_i, \overline{C_i X_j}\}_{i,j \in (0,1,2)}$ based on flag qubits. By adding a procedure for FT magic state preparation, we show quantitatively how to realize an FT universal gate set in $d=3$ LCS codes. Numerical simulations indicate that our gate constructions can attain pseudothresholds in the range $p_{\mathrm{th}} \approx 4.8\cdot 10^{-3}-1.2\cdot 10^{-2}$ for circuit-level noise. The schemes use a moderate number of qubits and are therefore feasible for near-term experiments, facilitating progress for fault-tolerant error corrected logic in high-rate qLPDC codes.

Comments
13 pages, 12 Figures

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Quantum low-density parity check (qLDPC) codes are among the leading candidates to realize error-corrected quantum memories with low qubit overhead. Potentially high encoding rates and large distance relative to their block size make them appealing for practical suppression of noise in near-term quantum computers. In addition to increased qubit-connectivity requirements compared to more conventional topological quantum error correcting codes, qLDPC codes remain notoriously hard to compute with. In this work, we introduce a construction to implement all Clifford quantum gate operations on the recently introduced lift-connected surface (LCS) codes (Old et al. 2024). These codes can be implemented in a 3D-local architecture and achieve asymptotic scaling [[n,O(n1/3),O(n1/3)]][[n, \mathcal{O}(n^{1/3}), \mathcal{O}(n^{1/3})]][[n,O(n1/3),O(n1/3)]]. In particular, LCS codes realize favorable instances with small numbers of qubits: For the [[15,3,3]][[15,3,3]][[15,3,3]] LCS code, we provide deterministic fault-tolerant (FT) circuits of the logical gate set {H‾i,H‾i,CiXj‾}i,j∈(0,1,2)\{\overline{H}_i, \overline{H}_i, \overline{C_i X_j}\}_{i,j \in (0,1,2)}{Hi​,Hi​,Ci​Xj​​}i,j∈(0,1,2)​ based on flag qubits. By adding a procedure for FT magic state preparation, we show quantitatively how to realize an FT universal gate set in d=3d=3d=3 LCS codes. Numerical simulations indicate that our gate constructions can attain pseudothresholds in the range pth≈4.8⋅10−3−1.2⋅10−2p_{\mathrm{th}} \approx 4.8\cdot 10^{-3}-1.2\cdot 10^{-2}pth​≈4.8⋅10−3−1.2⋅10−2 for circuit-level noise. The schemes use a moderate number of qubits and are therefore feasible for near-term experiments, facilitating progress for fault-tolerant error corrected logic in high-rate qLPDC codes.
Quantum low-density parity-check (qLDPC) codes can achieve high encoding rates and good code distance scaling, providing a promising route to low-overhead fault-tolerant quantum computing. However, the long-range connectivity required to implement such codes makes their physical realization challenging. Here, we propose a hardware-efficient scheme to perform fault-tolerant quantum computation with high-rate qLDPC codes on reconfigurable atom arrays, directly compatible with recently demonstrated experimental capabilities. Our approach utilizes the product structure inherent in many qLDPC codes to implement the non-local syndrome extraction circuit via atom rearrangement, resulting in effectively constant overhead in practically relevant regimes. We prove the fault tolerance of these protocols, perform circuit-level simulations of memory and logical operations with these codes, and find that our qLDPC-based architecture starts to outperform the surface code with as few as several hundred physical qubits at a realistic physical error rate of 10−310^{-3}10−3. We further find that less than 3000 physical qubits are sufficient to obtain over an order of magnitude qubit savings compared to the surface code, and quantum algorithms involving thousands of logical qubits can be performed using less than 10510^5105 physical qubits. Our work paves the way for explorations of low-overhead quantum computing with qLDPC codes at a practical scale, based on current experimental technologies.
Abstract We use the recently introduced lifted product to construct a family of quantum low density parity check codes (QLDPC codes). The codes we obtain can be viewed as stacks of surface codes that are interconnected, leading to the name lift-connected surface (LCS) codes. LCS codes offer a wide range of parameters—a particularly striking feature is that they show interesting properties that are favorable compared to the standard surface code. For example, already at moderate numbers of physical qubits in the order of tens, LCS codes of equal size have lower logical error rate or similarly, require fewer qubits for a fixed target logical error rate. We present and analyze the construction and provide numerical simulation results for the logical error rate under code capacity and phenomenological noise. These results show that LCS codes attain thresholds that are comparable to corresponding (non-connected) copies of surface codes, while the logical error rate can be orders of magnitude lower, even for representatives with the same parameters. This provides a code family showing the potential of modern product constructions at already small qubit numbers. Their amenability to 3D-local connectivity renders them particularly relevant for near-term implementations.
Quantum error correction is essential for building utility-scale quantum computers that outperform classical machines, yet leading approaches incur substantial physical qubit overhead. Quantum low-density parity check (QLDPC) codes offer a promising alternative by significantly reducing the number of physical qubits required per logical qubit. However, existing work on QLDPC codes has focused primarily on quantum memories, with no efficient method known for implementing arbitrary logical Clifford operations at low circuit depth. Here, we introduce a new family of QLDPC codes that enables efficient implementation of the full Clifford group via transversal operations, allowing any m-qubit Clifford operation to be executed in at most O(m) syndrome extraction rounds. We run circuit-level simulations of depth-126 logical circuits to demonstrate the near-memory logical performance of these logical operations. In combination with known methods for implementing T gates, these results establish QLDPC codes as a viable route toward resource-efficient universal quantum computation. Quantum LDPC codes can shield quantum computers from decoherence with minimal overhead. In this work, the authors describe a new QLDPC family, SHYPS, as a path to practical fault tolerance with efficient Clifford circuit implementation on encoded states.
The surface code is a promising route towards large-scale quantum computing, requiring only nearest-neighbour gates amenable to superconducting hardware. However, surface codes incur large qubit overheads. Novel quantum low-density parity check (qLDPC) codes promise to reduce overheads but require long-range connections that are difficult to achieve on superconducting platforms. Here, we introduce "Vine Codes" - qLDPC codes that are implementable on a planar square grid through nearest-neighbour, two-qubit gates native to superconducting platforms (iSWAP and CZ). Our approach generalises "Directional Codes" recently introduced by Gehér et. al. (2025) which are constrained to a torus. In contrast, vine codes have open boundary conditions constructed with the aid of routing qubits. We perform extensive numeric searches and find promising candidate vine codes, e.g. [[121,4,6]], [[221,6,7]], and [[234,9,6]] codes. We verify the circuit distances and show that data and measure qubits required can be reduced by up to ~28% relative to the surface code at a circuit distance of 7. Even including routing qubits, vine codes require fewer total qubits than the surface code (e.g. ~18% reduction at circuit distance 10) and benefits are expected to increase at higher distances. We perform circuit-level noise simulations to demonstrate that under a realistic noise model and at a near-term noise rate of 10−310^{-3}10−3, vine codes can perform better than the surface code while using fewer qubits. We give an exhaustive list of all unique vine codes up to stabiliser-weight 9. We additionally introduce "Flip-Vine Codes" which possess single-qubit transversal Clifford gates useful for fault-tolerant logic and magic state cultivation. We furthermore construct examples of generalised open boundaries for vine codes that go beyond the familiar X/Z boundaries of the surface and tile codes.
Quantum computing relies on quantum error correction for high-fidelity logical operations, but scaling to achieve near-term quantum utility is highly resource-intensive. High-rate quantum LDPC codes can reduce error correction overhead, yet realizing high-rate fault-tolerant computation with these codes remains a central challenge. Apart of the lattice surgery approach, standard schemes for realizing logical gates have so far been restricted to performing global operations on all logical qubits at the same time. Another approach relies on low-rate code switching methods. In this work, we introduce a gate-based protocol for addressable single- and multi-qubit Clifford operations on individual logical qubits encoded within one or more quantum LDPC codes. Our scheme leverages logical transversal operations via an auxiliary Bacon-Shor code to perform logical operations with constant time overhead enabled by teleportation. We demonstrate the implementation of an overcomplete logical Clifford gate set and perform numerical simulations to evaluate the error-correction performance of our protocol. Finally, we observe that our scheme can be integrated with magic state cultivation protocols to achieve universal, gate-based, and fully addressable quantum computation.
Topological quantum codes are intrinsically fault-tolerant to local noise, and underlie the theory of topological phases of matter. We explore geometry to enhance the performance of topological quantum codes by rotating the four dimensional self-correcting quantum memory, and present codes targeted to both near-term and utility-scale quantum computers. We identify a full set of logical Clifford operations and with it design a universal fault-tolerant quantum architecture. Our design achieves single-shot error correction, significant reductions in required qubits, and low-depth logical operations. In turn, our proposed architecture relaxes the requirements for achieving fault tolerance and offers an efficient path for realization in several near-term quantum hardware implementations. Our [[96,6,8]] 4D Hadamard lattice code has low weight-6 stabilizers and depth-8 syndrome extraction circuits, a high pseudo-threshold of ∼0.01\sim 0.01∼0.01, and a logical error rate of ∼10−6\sim 10^{-6}∼10−6 per logical qubit per round of error correction at 10−310^{-3}10−3 physical error rate under a standard circuit-level noise model. A Clifford-complete logical gate set is presented, including a constructive and efficient method for Clifford gate synthesis.