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arXiv:2606.20263

Vine Codes: Low-Overhead Quantum LDPC Codes on a Planar Square Grid

Georgia M. Nixon, Campbell K. McLauchlan, Charles C. L. van Rest

quant-phcond-mat.str-elSubmitted Jun 18, 2026• Announced Jun 19, 2026• 0 citations
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Abstract

The surface code is a promising route towards large-scale quantum computing, requiring only nearest-neighbour gates amenable to superconducting hardware. However, surface codes incur large qubit overheads. Novel quantum low-density parity check (qLDPC) codes promise to reduce overheads but require long-range connections that are difficult to achieve on superconducting platforms. Here, we introduce "Vine Codes" - qLDPC codes that are implementable on a planar square grid through nearest-neighbour, two-qubit gates native to superconducting platforms (iSWAP and CZ). Our approach generalises "Directional Codes" recently introduced by Gehér et. al. (2025) which are constrained to a torus. In contrast, vine codes have open boundary conditions constructed with the aid of routing qubits. We perform extensive numeric searches and find promising candidate vine codes, e.g. [[121,4,6]], [[221,6,7]], and [[234,9,6]] codes. We verify the circuit distances and show that data and measure qubits required can be reduced by up to ~28% relative to the surface code at a circuit distance of 7. Even including routing qubits, vine codes require fewer total qubits than the surface code (e.g. ~18% reduction at circuit distance 10) and benefits are expected to increase at higher distances. We perform circuit-level noise simulations to demonstrate that under a realistic noise model and at a near-term noise rate of $10^{-3}$, vine codes can perform better than the surface code while using fewer qubits. We give an exhaustive list of all unique vine codes up to stabiliser-weight 9. We additionally introduce "Flip-Vine Codes" which possess single-qubit transversal Clifford gates useful for fault-tolerant logic and magic state cultivation. We furthermore construct examples of generalised open boundaries for vine codes that go beyond the familiar X/Z boundaries of the surface and tile codes.

Comments
26 pages, 14 figures, 4 tables; supplementary data available on Zenodo

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High-performance quantum low-density parity-check codes promise substantial reductions in the overhead of fault-tolerant quantum computation, but most constructions require long-range connectivity or qubit shuttling, both of which are difficult to realise in superconducting architectures. Here we introduce a family of quantum low-density parity-check codes that, for the first time, combines planar open-boundary layouts, finite-size advantages over surface codes, and syndrome extraction using only nearest-neighbour gates on a planar grid of qubits with either square or hexagonal connectivity. The resulting circuits achieve optimal constant-depth stabiliser measurement, independent of code size, and naturally remove leakage from the system by exchanging the roles of check and data qubits at each syndrome extraction round. We find finite-size instances such as a [[323,14,15]] code, whose code-efficiency ratio is nearly an order of magnitude larger than that of rotated surface-code patches. At around 40 circuit qubits per logical qubit, the best directional tile-code layouts reduce the per-logical per-round logical error rate by a factor of 100 relative to rotated surface-code memories. These results show that the advantages of quantum low-density parity-check codes can survive compilation into strictly planar nearest-neighbour circuits, bringing low-overhead fault-tolerant memories closer to near-term hardware.
The major challenge on the way to fault-tolerant quantum computing comes from the insufficient quality of hardware components and the difficulty of scaling their number without further compromising fidelity. Quantum Low-Density Parity-Check (qLDPC) codes offer a promising solution by encoding logical qubits with low overhead and at a comparatively high code distance. However, it remains an open question how to scalably implement efficient qLDPC codes on fixed-connectivity quantum chips without increasing hardware complexity to enable the non-local interactions in their underlying QEC cycles. We resolve this challenge for the first time by introducing a family of qLDPC "barbell" codes accompanied by a realistic chip layout that natively supports all required two-qubit interactions. Crucially, the hardware complexity required to implement barbell codes remains constant as code distance increases. We provide a detailed investigation into the feasibility of all required hardware components and simulate a specific family of barbell codes against circuit-level noise. We find that, with a modest overhead of <30<30<30 data qubits per logical qubit, barbell codes can preserve information at a physical noise strength of 10−410^{-4}10−4 for several trillion QEC cycles. Simulations of logical multi-Pauli measurements, performed with circuits tailored to the chip, yield similar logical performance per QEC round, indicating that entangling gates between logical qubits in barbell codes can be realized fault-tolerantly.
Quantum low-density parity check (qLDPC) codes are among the leading candidates to realize error-corrected quantum memories with low qubit overhead. Potentially high encoding rates and large distance relative to their block size make them appealing for practical suppression of noise in near-term quantum computers. In addition to increased qubit-connectivity requirements compared to more conventional topological quantum error correcting codes, qLDPC codes remain notoriously hard to compute with. In this work, we introduce a construction to implement all Clifford quantum gate operations on the recently introduced lift-connected surface (LCS) codes (Old et al. 2024). These codes can be implemented in a 3D-local architecture and achieve asymptotic scaling [[n,O(n1/3),O(n1/3)]][[n, \mathcal{O}(n^{1/3}), \mathcal{O}(n^{1/3})]][[n,O(n1/3),O(n1/3)]]. In particular, LCS codes realize favorable instances with small numbers of qubits: For the [[15,3,3]][[15,3,3]][[15,3,3]] LCS code, we provide deterministic fault-tolerant (FT) circuits of the logical gate set {H‾i,H‾i,CiXj‾}i,j∈(0,1,2)\{\overline{H}_i, \overline{H}_i, \overline{C_i X_j}\}_{i,j \in (0,1,2)}{Hi​,Hi​,Ci​Xj​​}i,j∈(0,1,2)​ based on flag qubits. By adding a procedure for FT magic state preparation, we show quantitatively how to realize an FT universal gate set in d=3d=3d=3 LCS codes. Numerical simulations indicate that our gate constructions can attain pseudothresholds in the range pth≈4.8⋅10−3−1.2⋅10−2p_{\mathrm{th}} \approx 4.8\cdot 10^{-3}-1.2\cdot 10^{-2}pth​≈4.8⋅10−3−1.2⋅10−2 for circuit-level noise. The schemes use a moderate number of qubits and are therefore feasible for near-term experiments, facilitating progress for fault-tolerant error corrected logic in high-rate qLPDC codes.
Quantum low-density parity-check (qLDPC) codes are promising candidates for realizing large-scale fault-tolerant quantum computing. Although many codes with favorable theoretical parameters have been developed, their practical adoption must take hardware implementability into account. For mainstream quantum platforms such as superconductors and neutral atoms, the connectivity, the length of non-local couplings, and the complexity of wiring or atom rearrangement are key factors that dictate the difficulty of hardware realization. Here, we propose a new family of qLDPC codes, termed routing codes. Within this family, we find explicit instances whose encoding rates are competitive to those of bivariate bicycle (BB) codes, while systematically reducing qubit connectivity, shortening the length of non-local couplings, and, crucially, making all non-local couplings mutually parallel. This parallelism translates into quantifiable benefits, substantially reducing wiring crossings in superconducting multi-layer architectures and simplifying the scheduling of atom movement in neutral-atom arrays. The weight-7 routing codes maintain a high threshold of 0.7\% and reduce the physical qubit overhead by approximately a factor of 8, compared to surface codes achieving a same logical error rate. Further increasing the weight to 11 yields a [[200, 24, 14]] and [[200, 16, 17]] codes with an encoding rate over 23 times that of the surface code, at the cost of a higher logical error rate. These results establish routing codes as a hardware-centric qLDPC family that bridges the gap between theoretical optimality and near-term physical feasibility.
Utility-scale quantum computing requires quantum error correction (QEC) to protect quantum information against noise. Currently, superconducting hardware is a promising candidate for achieving fault tolerance due to its fast gate times and feasible scalability. However, it is often restricted to two-dimensional nearest-neighbour connectivity, and therefore the variety of quantum low-density parity-check (qLDPC) codes that can be implemented on it without sacrificing QEC performance is believed to be greatly restricted. In this paper we construct a new family of qLDPC codes, which we call ``directional codes'', that outperforms the rotated toric code (RTC) while satisfying the connectivity requirements of the widely adopted square-grid, and some even the sparser hexagonal-grid, on a torus. The key idea is to utilise the iSWAP gate -- a native gate demonstrated on superconducting qubits -- to construct circuits that measure the stabilisers of these qLDPC codes without the need for additional connections. We numerically evaluate the performance of directional codes, encoding four, six, twelve and eighteen logical qubits, using a common superconducting-inspired circuit-level Pauli noise model. We also compare them to the RTC and to the bivariate bicycle (BB) codes, currently the two most popular quantum LDPC code families. As a concrete example, when evaluated with the Tesseract decoder with short beam setting, the best directional code family investigated achieves the same logical error rate as the RTC at physical error rate p=10−3p=10^{-3}p=10−3 but requires only a quarter to a third of the number of physical qubits. Our discovery opens a novel direction in QEC code design, suggesting that complex high-connectivity hardware may not be necessary for low-overhead fault-tolerant quantum computation.
Tile codes are a family of planar quantum low-density parity-check (qLDPC) codes with weight-6 stabilizers and open boundary conditions, offering an encoding efficiency kd2/nkd^2/nkd2/n of up to four times that of the surface code. In this work, we develop an exhaustive search algorithm for finding SWAP-based routing schemes that implement syndrome extraction for four tile-code families using only nearest-neighbor interactions on a two-dimensional square lattice, matching the connectivity of the surface code. Using explicitly constructed routed syndrome-extraction circuits decoded with BP+OSD, we estimate the circuit-level thresholds of these code families. For the SI1000 noise model, the threshold without such a connectivity constraint is obtained in a range 0.23%-0.31%, while it decreases to 0.11%-0.13% with routing, representing a reduction factor of around two to three. Despite this threshold penalty, our resource-footprint analysis shows that routed tile codes require fewer physical qubits per logical qubit than the surface code at sufficiently low physical error rates: Under the SI1000 noise model, we find a crossover near p∗≈0.08%p^*\approx 0.08\%p∗≈0.08%, below which routed tile codes become more qubit-efficient, with an advantage that grows monotonically as the physical error rate decreases.