Variational quantum circuits (VQCs) are typically evaluated at the logical design level when analyzing trainability. However, execution on real quantum devices requires hardware-aware compilation (transpilation) to satisfy qubit connectivity and native gate-set constraints. In this paper, we examine how transpilation can alter the gradient statistics. Using parameter-shift differentiation and gradient variance estimation, we compare logical and transpiled circuits across three representative ansatz families: EfficientSU2 (dense entanglement), TTN (tree tensor network), and RealAmplitudes (linear entanglement). We observe architecture-dependent trainability shifts where densely entangling circuits exhibit pronounced gradient reshaping in shallow regimes, structured tensor-network circuits remain comparatively robust, and linear architectures show mixed behavior. Deep circuits across all families display minimal sensitivity to hardware-aware compilation. These findings demonstrate that transpilation acts as an implicit structural transformation of the optimization landscape, motivating compilation-aware analysis and co-design for VQCs.
Variational quantum circuits (VQCs) are typically evaluated at the logical design level when analyzing trainability. However, execution on real quantum devices requires hardware-aware compilation (transpilation) to satisfy qubit connectivity and native gate-set constraints. In this paper, we examine how transpilation can alter the gradient statistics. Using parameter-shift differentiation and gradient variance estimation, we compare logical and transpiled circuits across three representative ansatz families: EfficientSU2 (dense entanglement), TTN (tree tensor network), and RealAmplitudes (linear entanglement). We observe architecture-dependent trainability shifts where densely entangling circuits exhibit pronounced gradient reshaping in shallow regimes, structured tensor-network circuits remain comparatively robust, and linear architectures show mixed behavior. Deep circuits across all families display minimal sensitivity to hardware-aware compilation. These findings demonstrate that transpilation acts as an implicit structural transformation of the optimization landscape, motivating compilation-aware analysis and co-design for VQCs.
Variational quantum algorithms (VQAs) rely on parameterized quantum circuits (PQCs), whose performance is governed by expressibility and trainability. Existing studies typically evaluate these properties at the logical circuit level, implicitly assuming that designed PQCs remain unchanged during hardware execution. In practice, however, hardware-aware transpilation modifies circuit structure through qubit mapping, routing, and basis decomposition, potentially altering PQC behavior. In this paper, we perform a systematic hardware-aware analysis of expressibility and trainability by comparing logical and transpiled PQCs across multiple ansatz families, qubit counts, and circuit depths. Expressibility is measured using fidelity-based KL divergence, while trainability is quantified through gradient variance. Our results show that transpilation acts as an implicit architectural perturbation, producing strongly ansatz-dependent effects. Expressibility deviations exceed upto 125% in some cases, while trainability variations reach up to 25%. Structured ansatzes are generally more robust, whereas highly entangled architectures are more sensitive to transpilation-induced transformations. We further show that transpilation can alter the commonly assumed expressibility-trainability trade-off, demonstrating that logical-level analyses may not reliably predict hardware-level behavior. These findings highlight the importance of hardware-aware evaluation for accurate characterization of VQAs.
Compiling time-evolution operators of the form U(t)=e−iHt into hardware-native gate sequences is a central bottleneck for digital quantum simulation on noisy intermediate-scale quantum (NISQ) devices. Generic transpilation treats U(t) as an arbitrary unitary, discarding the structure of Hamiltonian dynamics and producing circuits whose depth exceeds hardware coherence limits. We introduce a structure-aware compilation framework that treats product-formula decompositions as synthesis primitives rather than simulation approximations. The method combines (i) native placement of Hamiltonian terms onto the hardware coupling map, (ii) adaptive selection of Trotter blocks via a greedy discretization procedure, and (iii) variational refinement using a Trotter-initialized ansatz. Across Heisenberg, Ising, and XY models with n=3--8 qubits, the compiled circuits achieve fidelities F>0.996 with approximately linear scaling in the number of entangling gates, while generic synthesis produces circuits that are orders of magnitude deeper. On IBM Torino hardware, we observe a regime in which shorter approximate circuits outperform deeper exact decompositions: a 27-CX circuit achieves higher hardware fidelity (Fhw=0.987) than a 187-CX exact circuit. These results demonstrate that, in the NISQ regime, structure-aware approximate compilation can outperform exact structure-agnostic synthesis, providing a practical pathway for executing Hamiltonian dynamics without requiring pulse-level control.
Variational quantum circuits (VQCs) suffer from barren plateaus, where gradients vanish exponentially with system size, limiting effective optimization. While prior mitigation strategies focus on circuit design and initialization, the effect of circuit compression – specifically, which gates are removed – on trainability remains comparatively unexplored. In this work we study quantum gate pruning from a trainability perspective in a controlled, noiseless 6-qubit simulation testbed, and report numerical evidence that gate-selection criterion plays a substantial role in preserving the optimization landscape of compressed circuits. We propose Q-AGASP, a saliency-based pruning framework that ranks parameterized quantum gates using a combination of gradient-weight sensitivity and quantum activation, and introduce a Quantum Fisher Information (QFI)-motivated saliency variant that targets parameters associated with low gradient variance. Both approaches are applied through an iterative pruning schedule with frozen weights. Experiments on a hybrid quantum-classical model (6-qubit, 144-parameter VQC) show that saliency-guided pruning improves the gradient variance of the surviving parameters relative to uninformed methods – by 6–9 $\times $ at 90% gate sparsity in our tested regime – while random or magnitude-based pruning can produce near-zero gradient variance in some seeds. We further find that post-fine-tuning accuracy converges across methods under our 15-epoch fine-tuning budget, which suggests that accuracy and pre-fine-tuning gradient variance are complementary rather than interchangeable diagnostics, with accuracy becoming less discriminative precisely when the fine-tuning budget is generous relative to circuit size. To analyze how gate rankings evolve during compression we introduce saliency drift, a Spearman-rank-correlation-based metric, and derive a distribution-free bound relating the observed correlation to the magnitude of ranking reshuffles; drift increases with sparsity in our experiments, consistent with iterative recomputation capturing structural changes not visible to one-shot pruning. We are explicit that these findings are numerical observations from a single ansatz, qubit count, and dataset rather than architecture-independent theorems, and we discuss how ansatz topology, entanglement structure, and circuit depth would be expected to modulate them, together with the changes needed to extend the framework to noisy hardware and to chemistry-motivated ansätze.
Parameterized quantum circuits (PQCs) serve as a flexible framework for implementing various quantum algorithms, particularly in quantum machine learning and optimization tasks. However, their training is challenging due to both theoretical constraints and the inherent limitations in current quantum hardware. A judicious choice of PQC architecture is crucial for accurately representing the solution space, and for ensuring convergence in training. Several works introduced measures of expressibility and entangling capability for PQCs, and compared these metrics across different circuit structures, providing insights into how they impact performance and efficiency. However, these investigations often assumed idealized all-to-all qubit connectivity, which is not applicable to most hardware architectures. In practice, additional transpilation steps are performed prior to execution on hardware. The potential impact of better alignment of the PQC structure with the underlying native topology has in fact motivated introduction of hardware-efficient ansatze. In our work, we extend the methodology of measuring PQC efficiency to include more realistic quantum hardware models. We examine several popular hardware topologies, including hexagonal, square, circular, linear, and all-to-all. We evaluate the expressibility and entangling capability of circuits with different connectivity types and various arrangements of rotation gates. We assess the training performance of these PQC types in the context of a variational compiling procedure and identify the preferred gate patterns. This approach provides a more realistic evaluation of PQC performance, thus offering practical insights into their applications on existing quantum devices.
This study investigates classification performance and trainability of variational quantum classifiers on near-term noisy quantum hardware across circuit depth and qubit count regimes within the context of quantum computing and machine learning, an area of growing scientific importance given its implications for hybrid quantum-classical algorithm design and practical NISQ hardware benchmarking for near-term quantum advantage assessment. Using gradient-based parameter optimization of parameterized quantum circuits with hardware noise modeling via density matrix simulation and physical execution on IBM Eagle processors, we examine expressibility of parameterized circuits enabling nonlinear decision boundaries in feature Hilbert space, with trainability constrained by barren plateau gradients at large qubit counts in 96 circuit architectures (4 qubit counts x 4 depths x 6 ansatz families) evaluated across 5 classification datasets with 20 random initialization seeds each drawn from IBM Quantum Eagle (127-qubit) and Falcon (27-qubit) processors with noise mitigation via zero-noise extrapolation. Results indicate that 10-qubit, 4-layer VQC achieves 84.2% classification accuracy on the best benchmark, within 3.8 percentage points of classical SVM, but gradient variance decays exponentially with qubit count (variance halving per 2 added qubits), confirming barren plateau scaling (p < 0.001), with 84.2% accuracy, 3.8 pp gap to classical SVM baseline as the primary quantitative benchmark. Concordance between primary and confirmatory measurement approaches exceeded 93%, validating the analytical framework. These findings contribute empirically to quantum computing and machine learning and carry actionable implications for the design of programs and policies targeting hybrid quantum-classical algorithm design and practical NISQ hardware benchmarking for near-term quantum advantage assessment.
Variational quantum compiling (VQC) algorithms aim to approximate deep quantum circuits with shallow parameterized ansatzes, making them more suitable for NISQ hardware. In this article a variant of VQC named the recursive variational quantum compiling (RVQC) algorithm is proposed. Existing VQC algorithms typically require coherently executing the full circuit during compilation. Under the influence of noise, sufficiently deep target circuits make compiling unfeasible using ordinary VQC. Since the compiling is often accomplished using a gradient-based quantum-classical approach, the quantum noise manifest as a noisy gradient during optimization, making convergence hard to obtain. On the other hand, RVQC can compile a circuit by first dividing it into N shorter sub-circuits, then evaluate one sub-circuit at a time. As a result, the circuit depth required to implement RVQC is not dependent on the depth of the target circuit, but on the depth of the sub-circuits. Choosing a high enough N thus ensures sufficiently shallow sub-circuit which can be successfully compiled individually. We show mathematical evidence of this property. RVQC was compared with VQC on a noise model of the IBM Santiago device with the goal of compiling several randomly generated five-qubit circuits of approximately depth 1000. It was shown that VQC was not able to converge within 500 iterations of optimization. On the other hand, RVQC was able to converge to a fidelity of 0.90±0.05 within a total of 500 iterations when splitting the target circuits into N=5 parts. We argue that this comes as a result of the mitigation of noise-induced barren plateaus.