Parameterized quantum circuits (PQCs) serve as a flexible framework for implementing various quantum algorithms, particularly in quantum machine learning and optimization tasks. However, their training is challenging due to both theoretical constraints and the inherent limitations in current quantum hardware. A judicious choice of PQC architecture is crucial for accurately representing the solution space, and for ensuring convergence in training. Several works introduced measures of expressibility and entangling capability for PQCs, and compared these metrics across different circuit structures, providing insights into how they impact performance and efficiency. However, these investigations often assumed idealized all-to-all qubit connectivity, which is not applicable to most hardware architectures. In practice, additional transpilation steps are performed prior to execution on hardware. The potential impact of better alignment of the PQC structure with the underlying native topology has in fact motivated introduction of hardware-efficient ansatze. In our work, we extend the methodology of measuring PQC efficiency to include more realistic quantum hardware models. We examine several popular hardware topologies, including hexagonal, square, circular, linear, and all-to-all. We evaluate the expressibility and entangling capability of circuits with different connectivity types and various arrangements of rotation gates. We assess the training performance of these PQC types in the context of a variational compiling procedure and identify the preferred gate patterns. This approach provides a more realistic evaluation of PQC performance, thus offering practical insights into their applications on existing quantum devices.
Parameterized quantum circuits (PQCs) serve as a flexible framework for implementing various quantum algorithms, particularly in quantum machine learning and optimization tasks. However, their training is challenging due to both theoretical constraints and the inherent limitations in current quantum hardware. A judicious choice of PQC architecture is crucial for accurately representing the solution space, and for ensuring convergence in training. Several works introduced measures of expressibility and entangling capability for PQCs, and compared these metrics across different circuit structures, providing insights into how they impact performance and efficiency. However, these investigations often assumed idealized all-to-all qubit connectivity, which is not applicable to most hardware architectures. In practice, additional transpilation steps are performed prior to execution on hardware. The potential impact of better alignment of the PQC structure with the underlying native topology has in fact motivated introduction of hardware-efficient ansatze. In our work, we extend the methodology of measuring PQC efficiency to include more realistic quantum hardware models. We examine several popular hardware topologies, including hexagonal, square, circular, linear, and all-to-all. We evaluate the expressibility and entangling capability of circuits with different connectivity types and various arrangements of rotation gates. We assess the training performance of these PQC types in the context of a variational compiling procedure and identify the preferred gate patterns. This approach provides a more realistic evaluation of PQC performance, thus offering practical insights into their applications on existing quantum devices.
Variational quantum algorithms (VQAs) rely on parameterized quantum circuits (PQCs), whose performance is governed by expressibility and trainability. Existing studies typically evaluate these properties at the logical circuit level, implicitly assuming that designed PQCs remain unchanged during hardware execution. In practice, however, hardware-aware transpilation modifies circuit structure through qubit mapping, routing, and basis decomposition, potentially altering PQC behavior. In this paper, we perform a systematic hardware-aware analysis of expressibility and trainability by comparing logical and transpiled PQCs across multiple ansatz families, qubit counts, and circuit depths. Expressibility is measured using fidelity-based KL divergence, while trainability is quantified through gradient variance. Our results show that transpilation acts as an implicit architectural perturbation, producing strongly ansatz-dependent effects. Expressibility deviations exceed upto 125% in some cases, while trainability variations reach up to 25%. Structured ansatzes are generally more robust, whereas highly entangled architectures are more sensitive to transpilation-induced transformations. We further show that transpilation can alter the commonly assumed expressibility-trainability trade-off, demonstrating that logical-level analyses may not reliably predict hardware-level behavior. These findings highlight the importance of hardware-aware evaluation for accurate characterization of VQAs.
Abstract Parameterized quantum circuits (PQCs) play an essential role in the performance of many variational quantum algorithms. One challenge in implementing such algorithms is choosing an effective circuit that well represents the solution space while maintaining a low circuit depth and parameter count. To characterize and identify expressible, yet compact, circuits, several descriptors are proposed, including expressibility and entangling capability, that are statistically estimated from classical simulations. These descriptors are computed for different circuit structures, varying the qubit connectivity and selection of gates. From these simulations, circuit fragments that perform well with respect to the descriptors are identified. In particular, a substantial improvement in performance of two‐qubit gates in a ring or all‐to‐all connected arrangement, compared to that of those on a line, is observed. Furthermore, improvement in both descriptors is achieved by sequences of controlled X‐rotation gates compared to sequences of controlled Z‐rotation gates. In addition, it is investigated how expressibility “saturates” with increased circuit depth, finding that the rate and saturated value appear to be distinguishing features of a PQC. While the correlation between each descriptor and algorithm performance remains to be investigated, methods and results from this study can be useful for algorithm development and design of experiments.
Parameterized quantum circuits~(PQCs) constitute a central building block of variational quantum algorithms~(VQAs) and quantum machine learning~(QML) methods. Existing ansatz designs often adopt hardware-agnostic or simplified 1D chain/ring entanglement patterns. However, as quantum hardware continues to develop, native 2D connectivity patterns, such as planar superconducting-qubit architectures, are becoming increasingly important. Inspired by this hardware structure, we construct a native 2D pairwise ansatz and compare its expressibility and trainability with representative 1D ansatze at identical layer depths, despite their different circuit depths. For the fixed 16-qubit system, the 2D ansatz has the smallest KL divergence at L=1 and 2, and its second-order frame potential approaches the theoretical lower bound more rapidly at shallow layer counts than the frame potentials of the three 1D ansatze. We also evaluate the gradient variance of the Pauli-Z-string expectation value ⟨Z0⊗⋯⊗Z15⟩ with respect to the first Ry angle. For this Pauli-Z string and fixed parameter, the gradient variance is smaller for the 2D circuit at L=1--4. The differences narrow at L=5, and the four ansatze yield statistically compatible variances at L=6.
Expressibility is a crucial factor of a Parameterized Quantum Circuit (PQC). In the context of Variational Quantum Algorithms (VQA) based Quantum Machine Learning (QML), a QML model composed of highly expressible PQC and sufficient number of qubits is theoretically capable of approximating any arbitrary continuous function. While much research has explored the relationship between expressibility and learning performance, as well as the number of layers in PQCs, the connection between expressibility and PQC structure has received comparatively less attention. In this paper, we analyze the connection between expressibility and the types of quantum gates within PQCs using a Gradient Boosting Tree model and SHapley Additive exPlanations (SHAP) values. Our analysis is performed on 1,615 instances of PQC derived from 19 PQC topologies, each with 2-18 qubits and 1-5 layers. The findings of our analysis provide guidance for designing highly expressible PQCs, suggesting the integration of more RX or RY gates while maintaining a careful balance with the number of CNOT gates. Furthermore, our evaluation offers an additional evidence of expressibility saturation, as observed by previous studies.
Parameterized quantum circuits (PQCs) are fundamental to quantum machine learning (QML), quantum optimization, and variational quantum algorithms (VQAs). The expressibility of PQCs is a measure that determines their capability to harness the full potential of the quantum state space. It is thus a crucial guidepost to know when selecting a particular PQC ansatz. However, the existing technique for expressibility computation through statistical estimation requires a large number of samples, which poses significant challenges due to time and computational resource constraints. This paper introduces a novel approach for expressibility estimation of PQCs using Graph Neural Networks (GNNs). We demonstrate the predictive power of our GNN model with a dataset consisting of 25,000 samples from the noiseless IBM QASM Simulator and 12,000 samples from three distinct noisy quantum backends. The model accurately estimates expressibility, with root mean square errors (RMSE) of 0.05 and 0.06 for the noiseless and noisy backends, respectively. We compare our model's predictions with reference circuits from Sim et al. and IBM Qiskit's hardware-efficient ansatz sets to further evaluate our model's performance. Our experimental evaluation in noiseless and noisy scenarios reveals a close alignment with ground truth expressibility values, highlighting the model's efficacy. Moreover, our model exhibits promising extrapolation capabilities, predicting expressibility values with low RMSE for out-of-range qubit circuits trained solely on only up to 5-qubit circuit sets. This work thus provides a reliable means of efficiently evaluating the expressibility of diverse PQCs on noiseless simulators and hardware.
Abstract Noisy Intermediate-Scale Quantum (NISQ) devices are near-term quantum computing devices that inherently suffer from imperfect gate implementation, decoherence, and measurement noise. The main type of variational quantum algorithms(VQAs) is based on Parameterized Quantum Circuits (PQCs), which, however, face practical challenges due to optimization instability of optimization caused by noise and reduced performance. In this paper, we suggest a comprehensive noise-resilient optimization framework for PQCs, which explicitly incorporates noise-resilient circuit architecture design, incorporating noise-aware training strategies into the variational optimization loop. The framework uses circuit structures that are efficient in depth and are hardware compatible in addition to adaptive optimizer choice, stochastic optimization, and averaging as a part of repeated measurement to reduce the impacts of realistic noise. Large-scale experiments are performed with different amounts of qubits, depths of the circuit and noise strengths with realistic noise models. The findings indicate that the convergence rate is faster, the stability is increased, the variability of run-to-run variability is minimized, and other robustness is better than the noise-unaware optimization techniques. Moreover, systematic studies determine optimal operating regions that optimally trade-off expressibility and noise tolerance to offer useful design advice on trusted implementation of VQAs with near-term quantum hardware.