Partially Fault-Tolerant Quantum Computation for Megaquop Applications
Ming-Zhi Chung, Ali H. Z. Kavaki, Artur Scherer, Abdullah Khalid, Xiangzhou Kong, Toru Kawakubo, Namit Anand, Gebremedhin A Dagnew, Zachary Webb, Allyson Silva, Gaurav Gyawali, Tennin Yan, Keisuke Fujii, Alan Ho, Masoud Mohseni, Pooya Ronagh, John Martinis
quant-phSubmitted Mar 13, 2026• Announced Mar 16, 2026• 0 citations
Partially fault-tolerant quantum computing (FTQC) has recently emerged as a promising approach for the execution of megaquop-scale circuits with millions of logical operations. In this work, we demonstrate the strengths and the limitations of this approach by conducting quantum resource estimation (QRE) of the space--time-efficient analog rotation (STAR) architecture using realistic hardware specifications for superconducting processors, and compare it against the QRE of the full FTQC architecture. We show how the performance of the STAR architecture's protocols is affected by hardware improvements. We also reduce the space requirements for partial FTQC by developing a procedure leveraging code growth to decrease the size of a factory producing analog rotation states. Our results reveal a non-trivial dependence of the optimal pre-growth code distance on the rotation angle with respect to post-growth infidelity. Further, we analyze space--time trade-offs between the factory size and the error-mitigation overhead, and observe that in an application-agnostic setting, there is a Goldilocks zone for circuits in the regime of roughly $10^5$--$10^6$ small-angle rotation gates. We show that quantum simulation of 2D Fermi--Hubbard model systems is a particularly well-suited application for the STAR architecture, requiring only hundreds of thousands of physical qubits and runtimes on the order of minutes for modest system sizes. Due to its favourable algorithmic scaling to larger system sizes, utility-scale simulation of the 2D Fermi--Hubbard model could potentially be attained using partial FTQC.
Partially fault-tolerant quantum computing (FTQC) has recently emerged as a promising approach for the execution of megaquop-scale circuits with millions of logical operations. In this work, we demonstrate the strengths and the limitations of this approach by conducting quantum resource estimation (QRE) of the space--time-efficient analog rotation (STAR) architecture using realistic hardware specifications for superconducting processors, and compare it against the QRE of the full FTQC architecture. We show how the performance of the STAR architecture's protocols is affected by hardware improvements. We also reduce the space requirements for partial FTQC by developing a procedure leveraging code growth to decrease the size of a factory producing analog rotation states. Our results reveal a non-trivial dependence of the optimal pre-growth code distance on the rotation angle with respect to post-growth infidelity. Further, we analyze space--time trade-offs between the factory size and the error-mitigation overhead, and observe that in an application-agnostic setting, there is a Goldilocks zone for circuits in the regime of roughly 105--106 small-angle rotation gates. We show that quantum simulation of 2D Fermi--Hubbard model systems is a particularly well-suited application for the STAR architecture, requiring only hundreds of thousands of physical qubits and runtimes on the order of minutes for modest system sizes. Due to its favourable algorithmic scaling to larger system sizes, utility-scale simulation of the 2D Fermi--Hubbard model could potentially be attained using partial FTQC.
Achieving practical quantum speedup with limited resources is a crucial challenge in both academic and industrial communities. To address this, a partially fault-tolerant quantum computing architecture called “space-time efficient analog rotation quantum computing architecture” (STAR architecture) been recently been proposed. This architecture focuses on minimizing resource requirements while maximizing the precision of non-Clifford gates, essential for universal quantum computation. However, nondeterministic processes such as the repeat-until-success (RUS) protocol and state injection can introduce significant computational overhead. Therefore, optimizing the logical circuit to minimize this overhead by using efficient fault-tolerant operations is essential. This paper presents an efficient method for simulating the time evolution of the two-dimensional (2D) Hubbard-model Hamiltonian, a promising application of the STAR architecture. We present two techniques, the parallel-injection protocol and adaptive injection-region updating, to reduce unnecessary time overhead specific to our architecture. By integrating these with the existing fermionic (f) technique, we develop an efficient Trotter-based time-evolution operation for the 2D Hubbard model. Our analysis reveals an acceleration of over 10 times compared to naive serial compilation. Based on this optimized compilation, we estimate the computational resources required for the quantum phase estimation of the 2D Hubbard model. For devices with a physical error rate of p phys = 10 − 4 , we estimate that approximately 6.2 × 10 4 physical qubits are required to achieve faster ground-state energy estimation of the 8 × 8 Hubbard model compared to classical computation.
Quantum computers hold the promise of revolutionizing several computational tasks by significantly enhancing their calculation speed compared to classical computers. However, there is still a large gap towards fault-tolerant quantum computing (FTQC) due to the large requirement of physical qubits. Under these circumstances, authors proposed a partially fault-tolerant quantum computing architecture that consists of the fault-tolerant Clifford gates and the sufficiently clean analog rotation gate, named “Space-Time efficient Analog Rotation gate quantum computing architecture (STAR architecture).” Although its theoretical foundation is given, we need to develop an efficient software implementation tailored for STAR architecture due to its unique choice of the fundamental gate set. In this study, we construct an integrated software system of STAR-architecture-based quantum computation, which generates physical instructions executable on quantum devices from input logical quantum circuits. The system mainly consists of two parts, a circuit converter and an operation controller. The circuit converter comprises a set of conversion subroutines, which bridge several instruction layers: logical circuit layer, lattice surgery layer, and physical circuit layer. The operation controller efficiently executes the generated instructions. Especially, it enables efficient treatment of the analog rotation gate, which needs real-time scheduling of running instructions due to its probabilistic nature.
Fault-tolerant (FT) quantum computation offers a pathway to quantum advantage, but its realization is hindered by its significant overhead. The partially FT "STAR" architecture reduces the cost of universal computation at the price of relaxing FT requirements for non-Clifford operations, increasing exposure to hardware noise. Therefore, maximizing its performance and applicability demands careful co-design with the underlying hardware. In this work we investigate the co-design of the STAR architecture with neutral-atom platforms, connecting the underlying atomic physics to logical error modeling and application-level performance. At the physical level, we identify a favorable noise bias in 171Yb Rydberg gates, and show how it can be enhanced through error-selective pulse optimization. At the logical level, we identify an intrinsic error suppression mechanism, yielding vanishing logical coherent noise in leading order. Detailed circuit-level simulations of surface code implementations show more than an order of magnitude reduction in logical error relative to previous estimates. As a concrete target application, we focus on the Fermi-Hubbard model with periodic boundaries, for which we design a simulation circuit particularly suited to early implementations. We quantify the resource tradeoff of partially and fully FT approaches to gate synthesis, with the former showing approximately an order of magnitude reduction in state-injection depth, and an even larger reduction in Clifford resources. Comparing with classical and fully FT approaches, we identify regimes where partial fault tolerance provides both lower overheads and lower error rates. In our estimates, this is accessible with moderate error rates p∼10−3 and a few thousand qubits, underlining that for these types of problems, partial FT approaches provide a compelling pathway to early quantum advantage.
As we are entering an early-FTQC era, circuit execution protocols with logical qubits and certain error-correcting codes are being discussed. Here, we propose a circuit execution protocol for the space-time efficient analog rotation (STAR) architecture. Gate operations within the STAR architecture is based on lattice surgery with surface codes, but it allows direct execution of continuous gates Rz(θ) as non-Clifford gates instead of T=Rz(π/4). Rz(θ) operations involve creation of resource states $|m_θ\rangle = \frac{1}{\sqrt{2}} (|0 \rangle + e^{iθ} |1\rangle ) $ followed by ZZ joint measurements with target logical qubits. While employing Rz(θ) enables more efficient circuit execution, both their creations and joint measurements are probabilistic processes and adopt repeat-until-success (RUS) protocols which are likely to result in considerable time overhead. Our circuit execution protocol aims to reduce such time overhead by parallel trials of resource state creations and more frequent trials of joint measurements. By employing quadratic unconstrained binary optimization (QUBO) in determining resource state allocations within the space, we successfully make our protocol efficient. Furthermore, we proposed performance estimators given the target circuit and qubit topology. It successfully predicts the time performance within less time than actual simulations do, and helps find the optimal qubit topology to run the target circuits efficiently.
Quantum computing experiments have made remarkable progress in demonstrating key components of error-corrected quantum computing, a prerequisite for scalable quantum computation. While we anticipate the near-term arrival of early fault-tolerant quantum hardware capable of a million reliable quantum operations, the cost of preparing low-noise “magic resource states,” which are necessary for performing universal quantum computation, presents a formidable challenge. The recently proposed partially fault-tolerant architecture based on a space-time efficient analog rotation (STAR) approach attempts to address this challenge by using postselection to prepare low-noise, arbitrary small-angle magic states. Its proposed physical implementation, however, assumes fixed qubit connectivity, resulting in implementation costs closer to leading fully fault-tolerant approaches. In this work, we propose the transversal STAR architecture and co-design it with neutral-atom quantum hardware, deriving explicit and significant savings in logical layout, time, and space overhead. Through detailed circuit-level simulations, we derive the logical noise model for surface-code-based transversal STAR gadgets and verify their composability. At its limit, the transversal STAR architecture with neutral atoms can efficiently simulate local Hamiltonians with a total simulation volume exceeding 600, defined as the product of the number of logical qubits and Hamiltonian evolution timescales. Achieving this limit would require approximately 10 000 physical qubits at a physical error rate of 10 − 3 . This is equivalent to a fully fault-tolerant computation requiring over 10 6 – 10 7 T gates and a potential > 100 × saving on space-time volume for equivalent simulation over current, state-of-the-art protocols. Finally, we extend the transversal STAR architecture to high-rate quantum low-density parity-check codes, demonstrating how a limited set of highly parallel transversal Clifford gates and generalized small-angle magic injection can be utilized for effective quantum simulation. We anticipate that the co-designed transversal STAR architecture could substantially reduce the physical resources necessary for early fault-tolerant quantum simulation at the megaquop scale.
Quantum simulation of molecular electronic structure is one of the most promising applications of quantum computing. However, achieving chemically accurate predictions for strongly correlated systems requires quantum phase estimation (QPE) on fault-tolerant quantum computing (FTQC) devices. Existing resource estimates for typical FTQC architectures suggest that such calculations demand millions of physical qubits, thereby placing them beyond the reach of near-term devices. Here, we investigate the feasibility of performing QPE for chemically relevant molecular systems in an early-FTQC regime, characterized by partial fault tolerance, constrained qubit budgets, and limited circuit depth. Our framework is based on single-ancilla, Trotter-based QPE implementations combined with partially randomized time evolution. Within this framework, we develop a novel Hamiltonian optimization strategy, termed unitary weight concentration, that reduces algorithmic cost by reshaping linear-combination-of-unitaries representations. Applying this framework to active-space models of iron-sulfur clusters, cytochrome P450 active sites, and CO2-utilization catalysts, we perform end-to-end resource estimation using the latest version of the space-time efficient analog rotation (STAR) architecture. Our results indicate that ground-state energy estimation for active spaces of approximately 20 to 50 spatial orbitals, well beyond the reach of classical full configuration interaction, is achievable using ∼105 physical qubits, with runtimes on the order of days to weeks. These findings demonstrate that while full-fledged fault-tolerant quantum computers will be required for even larger molecular simulations, chemically meaningful quantum chemistry problems are already within reach in an experimentally relevant, early-FTQC regime.