Quantum computers hold the promise of revolutionizing several computational tasks by significantly enhancing their calculation speed compared to classical computers. However, there is still a large gap towards fault-tolerant quantum computing (FTQC) due to the large requirement of physical qubits. Under these circumstances, authors proposed a partially fault-tolerant quantum computing architecture that consists of the fault-tolerant Clifford gates and the sufficiently clean analog rotation gate, named “Space-Time efficient Analog Rotation gate quantum computing architecture (STAR architecture).” Although its theoretical foundation is given, we need to develop an efficient software implementation tailored for STAR architecture due to its unique choice of the fundamental gate set. In this study, we construct an integrated software system of STAR-architecture-based quantum computation, which generates physical instructions executable on quantum devices from input logical quantum circuits. The system mainly consists of two parts, a circuit converter and an operation controller. The circuit converter comprises a set of conversion subroutines, which bridge several instruction layers: logical circuit layer, lattice surgery layer, and physical circuit layer. The operation controller efficiently executes the generated instructions. Especially, it enables efficient treatment of the analog rotation gate, which needs real-time scheduling of running instructions due to its probabilistic nature.
Partially fault-tolerant quantum computing (FTQC) has recently emerged as a promising approach for the execution of megaquop-scale circuits with millions of logical operations. In this work, we demonstrate the strengths and the limitations of this approach by conducting quantum resource estimation (QRE) of the space--time-efficient analog rotation (STAR) architecture using realistic hardware specifications for superconducting processors, and compare it against the QRE of the full FTQC architecture. We show how the performance of the STAR architecture's protocols is affected by hardware improvements. We also reduce the space requirements for partial FTQC by developing a procedure leveraging code growth to decrease the size of a factory producing analog rotation states. Our results reveal a non-trivial dependence of the optimal pre-growth code distance on the rotation angle with respect to post-growth infidelity. Further, we analyze space--time trade-offs between the factory size and the error-mitigation overhead, and observe that in an application-agnostic setting, there is a Goldilocks zone for circuits in the regime of roughly
105--
106 small-angle rotation gates. We show that quantum simulation of 2D Fermi--Hubbard model systems is a particularly well-suited application for the STAR architecture, requiring only hundreds of thousands of physical qubits and runtimes on the order of minutes for modest system sizes. Due to its favourable algorithmic scaling to larger system sizes, utility-scale simulation of the 2D Fermi--Hubbard model could potentially be attained using partial FTQC.
Quantum computers are expected to drastically accelerate certain computing tasks versus classical computers. Noisy intermediate-scale quantum (NISQ) devices, which have tens to hundreds of noisy physical qubits, are gradually becoming available, but it is still challenging to achieve useful quantum advantages in meaningful tasks. On the other hand, full fault-tolerant quantum computing (FTQC) based on quantum error correction code remains far beyond realization due to its extremely large requirement of high-precision physical qubits. In this study, we propose a quantum computing architecture to close the gap between NISQ and FTQC architectures. Our architecture is based on erroneous arbitrary rotation gates and error-corrected Clifford gates implemented by lattice surgery. We omit the typical distillation protocol to achieve direct analog rotations and small qubit requirements, and minimize the remnant errors of the rotations by a carefully designed state injection protocol. Our estimation based on numerical simulations shows that for early-FTQC devices that consist of 104 physical qubits with physical error probability p=10−4 , we can perform roughly 1.72×107 Clifford operations and 3.75×104 arbitrary rotations on 64 logical qubits. Such computations cannot be realized by the existing NISQ and FTQC architectures on the same device, as well as classical computers. We hope that our proposal and the corresponding development of quantum algorithms based on it will bring new insights into the realization of practical quantum computers in the future. Published by the American Physical Society 2024
As we are entering an early-FTQC era, circuit execution protocols with logical qubits and certain error-correcting codes are being discussed. Here, we propose a circuit execution protocol for the space-time efficient analog rotation (STAR) architecture. Gate operations within the STAR architecture is based on lattice surgery with surface codes, but it allows direct execution of continuous gates
Rz(θ) as non-Clifford gates instead of
T=Rz(π/4).
Rz(θ) operations involve creation of resource states $|m_θ\rangle = \frac{1}{\sqrt{2}} (|0 \rangle + e^{iθ} |1\rangle ) $ followed by ZZ joint measurements with target logical qubits. While employing
Rz(θ) enables more efficient circuit execution, both their creations and joint measurements are probabilistic processes and adopt repeat-until-success (RUS) protocols which are likely to result in considerable time overhead. Our circuit execution protocol aims to reduce such time overhead by parallel trials of resource state creations and more frequent trials of joint measurements. By employing quadratic unconstrained binary optimization (QUBO) in determining resource state allocations within the space, we successfully make our protocol efficient. Furthermore, we proposed performance estimators given the target circuit and qubit topology. It successfully predicts the time performance within less time than actual simulations do, and helps find the optimal qubit topology to run the target circuits efficiently.
We introduce STAR-magic mutation, an efficient protocol for implementing logical rotation gates on early fault-tolerant quantum computers. This protocol judiciously combines two of the latest state preparation protocols: transversal multi-rotation protocol and magic state cultivation. It achieves a logical rotation gate with a favorable error scaling of
O(θL2(1−Θ(1/d))pph), while requiring only the ancillary space of a single surface code patch. Here,
θL is the logical rotation angle,
pph is the physical error rate, and
d is the code distance. This scaling marks a significant improvement over the previous state-of-the-art,
O(θLpph), making our protocol particularly powerful for implementing a sequence of small-angle rotation gates, like Trotter-based circuits. Notably, for
θL≲10−5, our protocol achieves a two-order-of-magnitude reduction in both the execution time and the error rate of analog rotation gates compared to the standard
T-gate synthesis using cultivated magic states. Building upon this protocol, we also propose a novel quantum computing architecture designed for early fault-tolerant quantum computers, dubbed ``STAR ver.~3". It employs a refined circuit compilation strategy based on Clifford+
T+
φ gate set, rather than the conventional Clifford+
T or Clifford+
φ gate sets. We establish a theoretical bound on the feasible circuit size on this architecture and illustrate its capabilities by analyzing the spacetime costs for simulating the dynamics of quantum many-body systems. Specifically, we demonstrate that our architecture can simulate biologically-relevant molecules or lattice models at scales beyond the reach of exact classical simulation, with only a few hundred thousand physical qubits, even assuming a realistic error rate of
pph=10−3.
Scalable quantum computation is expected to rely on fault-tolerant quantum computation (FTQC), in which quantum error correction (QEC) suppresses physical errors sufficiently to support reliable logical operations. This requires quantum compilation to move beyond general-purpose circuit optimization toward encoding-aware and protocol-structured compilation across the full stack of fault-tolerant quantum computers. Beyond circuit synthesis and hardware mapping, an FTQC compiler must lower algorithm-level operations into the logical gate set supported by the chosen code, coordinate encoded data and ancilla resources, realize logical operations together with repeated syndrome extraction under hardware constraints, and provide the resulting measurement stream to real-time decoding.
This survey presents a full-stack view of compiler design for QEC-protected quantum computation. We organize existing work into three interacting layers: logical-level QEC compilation, physical-level QEC realization, and decoder runtime integration. At the logical level, we review surface-code lattice-surgery compilers, beyond-surface-code code-surgery frameworks including emerging qLDPC approaches, and compilation support for non-Clifford operations such as magic-state distillation and code switching. At the physical level, we survey hardware-aware QEC realization on superconducting, trapped-ion, and neutral-atom platforms. We further examine decoder models, real-time decoding systems, and frame-management mechanisms that close the feedback loop during fault-tolerant execution. Finally, we identify open challenges in cross-layer optimization, qLDPC compilation, compiler-decoder co-design, runtime adaptivity, and the development of integrated and benchmarkable FTQC compilation stacks. An actively maintained paper list is available at: github.com/chenghongz/QEC-compiler-design.
Achieving practical quantum speedup with limited resources is a crucial challenge in both academic and industrial communities. To address this, a partially fault-tolerant quantum computing architecture called “space-time efficient analog rotation quantum computing architecture” (STAR architecture) been recently been proposed. This architecture focuses on minimizing resource requirements while maximizing the precision of non-Clifford gates, essential for universal quantum computation. However, nondeterministic processes such as the repeat-until-success (RUS) protocol and state injection can introduce significant computational overhead. Therefore, optimizing the logical circuit to minimize this overhead by using efficient fault-tolerant operations is essential. This paper presents an efficient method for simulating the time evolution of the two-dimensional (2D) Hubbard-model Hamiltonian, a promising application of the STAR architecture. We present two techniques, the parallel-injection protocol and adaptive injection-region updating, to reduce unnecessary time overhead specific to our architecture. By integrating these with the existing fermionic (f) technique, we develop an efficient Trotter-based time-evolution operation for the 2D Hubbard model. Our analysis reveals an acceleration of over 10 times compared to naive serial compilation. Based on this optimized compilation, we estimate the computational resources required for the quantum phase estimation of the 2D Hubbard model. For devices with a physical error rate of p phys = 10 − 4 , we estimate that approximately 6.2 × 10 4 physical qubits are required to achieve faster ground-state energy estimation of the 8 × 8 Hubbard model compared to classical computation.