Achieving practical quantum speedup with limited resources is a crucial challenge in both academic and industrial communities. To address this, a partially fault-tolerant quantum computing architecture called “space-time efficient analog rotation quantum computing architecture” (STAR architecture) been recently been proposed. This architecture focuses on minimizing resource requirements while maximizing the precision of non-Clifford gates, essential for universal quantum computation. However, nondeterministic processes such as the repeat-until-success (RUS) protocol and state injection can introduce significant computational overhead. Therefore, optimizing the logical circuit to minimize this overhead by using efficient fault-tolerant operations is essential. This paper presents an efficient method for simulating the time evolution of the two-dimensional (2D) Hubbard-model Hamiltonian, a promising application of the STAR architecture. We present two techniques, the parallel-injection protocol and adaptive injection-region updating, to reduce unnecessary time overhead specific to our architecture. By integrating these with the existing fermionic (f) technique, we develop an efficient Trotter-based time-evolution operation for the 2D Hubbard model. Our analysis reveals an acceleration of over 10 times compared to naive serial compilation. Based on this optimized compilation, we estimate the computational resources required for the quantum phase estimation of the 2D Hubbard model. For devices with a physical error rate of p phys = 10 − 4 , we estimate that approximately 6.2 × 10 4 physical qubits are required to achieve faster ground-state energy estimation of the 8 × 8 Hubbard model compared to classical computation.
Partially fault-tolerant quantum computing (FTQC) has recently emerged as a promising approach for the execution of megaquop-scale circuits with millions of logical operations. In this work, we demonstrate the strengths and the limitations of this approach by conducting quantum resource estimation (QRE) of the space--time-efficient analog rotation (STAR) architecture using realistic hardware specifications for superconducting processors, and compare it against the QRE of the full FTQC architecture. We show how the performance of the STAR architecture's protocols is affected by hardware improvements. We also reduce the space requirements for partial FTQC by developing a procedure leveraging code growth to decrease the size of a factory producing analog rotation states. Our results reveal a non-trivial dependence of the optimal pre-growth code distance on the rotation angle with respect to post-growth infidelity. Further, we analyze space--time trade-offs between the factory size and the error-mitigation overhead, and observe that in an application-agnostic setting, there is a Goldilocks zone for circuits in the regime of roughly
105--
106 small-angle rotation gates. We show that quantum simulation of 2D Fermi--Hubbard model systems is a particularly well-suited application for the STAR architecture, requiring only hundreds of thousands of physical qubits and runtimes on the order of minutes for modest system sizes. Due to its favourable algorithmic scaling to larger system sizes, utility-scale simulation of the 2D Fermi--Hubbard model could potentially be attained using partial FTQC.
As we are entering an early-FTQC era, circuit execution protocols with logical qubits and certain error-correcting codes are being discussed. Here, we propose a circuit execution protocol for the space-time efficient analog rotation (STAR) architecture. Gate operations within the STAR architecture is based on lattice surgery with surface codes, but it allows direct execution of continuous gates
Rz(θ) as non-Clifford gates instead of
T=Rz(π/4).
Rz(θ) operations involve creation of resource states $|m_θ\rangle = \frac{1}{\sqrt{2}} (|0 \rangle + e^{iθ} |1\rangle ) $ followed by ZZ joint measurements with target logical qubits. While employing
Rz(θ) enables more efficient circuit execution, both their creations and joint measurements are probabilistic processes and adopt repeat-until-success (RUS) protocols which are likely to result in considerable time overhead. Our circuit execution protocol aims to reduce such time overhead by parallel trials of resource state creations and more frequent trials of joint measurements. By employing quadratic unconstrained binary optimization (QUBO) in determining resource state allocations within the space, we successfully make our protocol efficient. Furthermore, we proposed performance estimators given the target circuit and qubit topology. It successfully predicts the time performance within less time than actual simulations do, and helps find the optimal qubit topology to run the target circuits efficiently.
Achieving quantum speedups in practical tasks remains challenging for current noisy intermediate-scale quantum (NISQ) devices. These devices always encounter significant obstacles such as inevitable physical errors and the limited scalability of current near-term algorithms. Meanwhile, assuming a typical architecture for fault-tolerant quantum computing (FTQC), realistic applications inevitably require a vast number of qubits, typically exceeding 10 6 , which seems far beyond near-term realization. In this work, to bridge the gap between the NISQ and FTQC eras, we propose an alternative approach to achieve practical quantum advantages on early-FTQC devices. Our framework is based on partially fault-tolerant logical operations to minimize spatial overhead and avoids the costly distillation techniques typically required for executing non-Clifford gates. To this end, we develop a space-time efficient state preparation protocol to generate an ancillary non-Clifford state consumed for implementing an analog rotation gate with an arbitrary small angle θ and a remarkably low worst-case error rate below O ( | θ | p ph ) , where p ph is the physical error rate. Furthermore, we propose several error suppression schemes tailored to our preparation protocol, which are essential to minimize the overhead for mitigating errors. Based on this framework, we present several promising applications that leverage the potential of our framework, including the Trotter simulation and quantum phase estimation (QPE). Notably, we demonstrate that our framework allows us to perform the QPE for an ( 8 × 8 ) -site Hubbard model with fewer than 6.8 × 10 4 qubits and an execution time of 10.6 days (or 14 min with full parallelization) under p ph = 10 − 4 , which is significantly faster than recent classical estimation with tensor network techniques (density matrix renormalization group and projected entangled pair states).
We introduce STAR-magic mutation, an efficient protocol for implementing logical rotation gates on early fault-tolerant quantum computers. This protocol judiciously combines two of the latest state preparation protocols: transversal multi-rotation protocol and magic state cultivation. It achieves a logical rotation gate with a favorable error scaling of
O(θL2(1−Θ(1/d))pph), while requiring only the ancillary space of a single surface code patch. Here,
θL is the logical rotation angle,
pph is the physical error rate, and
d is the code distance. This scaling marks a significant improvement over the previous state-of-the-art,
O(θLpph), making our protocol particularly powerful for implementing a sequence of small-angle rotation gates, like Trotter-based circuits. Notably, for
θL≲10−5, our protocol achieves a two-order-of-magnitude reduction in both the execution time and the error rate of analog rotation gates compared to the standard
T-gate synthesis using cultivated magic states. Building upon this protocol, we also propose a novel quantum computing architecture designed for early fault-tolerant quantum computers, dubbed ``STAR ver.~3". It employs a refined circuit compilation strategy based on Clifford+
T+
φ gate set, rather than the conventional Clifford+
T or Clifford+
φ gate sets. We establish a theoretical bound on the feasible circuit size on this architecture and illustrate its capabilities by analyzing the spacetime costs for simulating the dynamics of quantum many-body systems. Specifically, we demonstrate that our architecture can simulate biologically-relevant molecules or lattice models at scales beyond the reach of exact classical simulation, with only a few hundred thousand physical qubits, even assuming a realistic error rate of
pph=10−3.
Fault-tolerant quantum simulation is approaching a phase where encoding overhead, logical Clifford operations, magic-state preparation, and rotation synthesis must be optimized together for efficient implementation. Space-Time efficient Analog Rotation (STAR) architectures reduce two of these costs by preparing small-angle rotation magic states directly, and the transversal STAR variant further lowers the Clifford overhead. Existing concrete implementations, however, largely inherit the low
O(1/d2) encoding rate of the surface code, while high-rate codes have not yet been integrated into comparably explicit architectures. Here, we introduce a high-rate STAR architecture for local lattice Hamiltonian simulation based on a symmetry-driven co-design of the algorithm, QEC code, and neutral-atom hardware. Translation symmetries of the target lattice determine the choice of bicycle chain codes, a tunable family of self-dual bivariate bicycle codes that natively implement Clifford gates required for lattice simulation. Disjoint logical representatives allow STAR injections to be performed in parallel on all
k logical qubits in a code block, amortizing resource state preparation and enabling practical post-selection rates. On neutral-atom platform, the same translation symmetry compiles the key logical operations into low-depth, hardware-native acousto-optic-deflector shifts. End-to-end estimates show that an
8×8 transverse-field Ising simulation to
T∗≈8(zJ)−1 requires
2240 physical qubits and
∼200 s per shot, a
∼5.5× space reduction relative to a surface code STAR baseline at comparable speed; for Fermi-Hubbard dynamics to
T∗≈4(zt)−1, the corresponding estimates are
∼6300 physical qubits and
∼200 s per shot. These results provide a concrete route toward early fault-tolerant quantum simulation with high-rate codes.
Fault-tolerant (FT) quantum computation offers a pathway to quantum advantage, but its realization is hindered by its significant overhead. The partially FT "STAR" architecture reduces the cost of universal computation at the price of relaxing FT requirements for non-Clifford operations, increasing exposure to hardware noise. Therefore, maximizing its performance and applicability demands careful co-design with the underlying hardware. In this work we investigate the co-design of the STAR architecture with neutral-atom platforms, connecting the underlying atomic physics to logical error modeling and application-level performance. At the physical level, we identify a favorable noise bias in
171Yb Rydberg gates, and show how it can be enhanced through error-selective pulse optimization. At the logical level, we identify an intrinsic error suppression mechanism, yielding vanishing logical coherent noise in leading order. Detailed circuit-level simulations of surface code implementations show more than an order of magnitude reduction in logical error relative to previous estimates. As a concrete target application, we focus on the Fermi-Hubbard model with periodic boundaries, for which we design a simulation circuit particularly suited to early implementations. We quantify the resource tradeoff of partially and fully FT approaches to gate synthesis, with the former showing approximately an order of magnitude reduction in state-injection depth, and an even larger reduction in Clifford resources. Comparing with classical and fully FT approaches, we identify regimes where partial fault tolerance provides both lower overheads and lower error rates. In our estimates, this is accessible with moderate error rates
p∼10−3 and a few thousand qubits, underlining that for these types of problems, partial FT approaches provide a compelling pathway to early quantum advantage.