Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Log inSign up
Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Blog
Job Board
Q3AS

© 2026 Aqora Quantum S.A.S.

TermsPrivacyLegal Notice

arXiv:2606.25011

Fast and Parallel High-Rate STAR Architecture for Megaquop Quantum Simulation

Refaat Ismail, Milan Kornjača, Hong-Ye Hu, Nishad Maskara, Sheng-Tao Wang, Hengyun Zhou, Chen Zhao

quant-phSubmitted Jun 23, 2026• Announced Jun 24, 2026• 0 citations
arXivHTMLPDF

Abstract

Fault-tolerant quantum simulation is approaching a phase where encoding overhead, logical Clifford operations, magic-state preparation, and rotation synthesis must be optimized together for efficient implementation. Space-Time efficient Analog Rotation (STAR) architectures reduce two of these costs by preparing small-angle rotation magic states directly, and the transversal STAR variant further lowers the Clifford overhead. Existing concrete implementations, however, largely inherit the low $O(1/d^2)$ encoding rate of the surface code, while high-rate codes have not yet been integrated into comparably explicit architectures. Here, we introduce a high-rate STAR architecture for local lattice Hamiltonian simulation based on a symmetry-driven co-design of the algorithm, QEC code, and neutral-atom hardware. Translation symmetries of the target lattice determine the choice of bicycle chain codes, a tunable family of self-dual bivariate bicycle codes that natively implement Clifford gates required for lattice simulation. Disjoint logical representatives allow STAR injections to be performed in parallel on all $k$ logical qubits in a code block, amortizing resource state preparation and enabling practical post-selection rates. On neutral-atom platform, the same translation symmetry compiles the key logical operations into low-depth, hardware-native acousto-optic-deflector shifts. End-to-end estimates show that an $8 \times 8$ transverse-field Ising simulation to $T^* \approx 8 (zJ)^{-1}$ requires $2240$ physical qubits and $\sim 200$ s per shot, a $\sim 5.5\times$ space reduction relative to a surface code STAR baseline at comparable speed; for Fermi-Hubbard dynamics to $T^* \approx 4 (zt)^{-1}$, the corresponding estimates are $\sim 6300$ physical qubits and $\sim 200$ s per shot. These results provide a concrete route toward early fault-tolerant quantum simulation with high-rate codes.

Related papers

STAR-Magic Mutation: Even More Efficient Analog Rotation Gates for Early Fault-Tolerant Quantum Computer

Riki Toshio, Shota Kanasugi, Jun Fujisaki +3 more

We introduce STAR-magic mutation, an efficient protocol for implementing logical rotation gates on early fault-tolerant quantum computers. This protocol judiciously combines two of the latest state preparation protocols: transversal multi-rotation protocol and magic state cultivation. It achieves a logical rotation gate with a favorable error scaling of $\mathcal{O}(θ_L^{2(1-Θ(1/d))}p_{\text{ph}})$, while requiring only the ancillary space of a single surface code patch. Here, $θ_L$ is the logical rotation angle, $p_{\text{ph}}$ is the physical error rate, and $d$ is the code distance. This scaling marks a significant improvement over the previous state-of-the-art, $\mathcal{O}(θ_L p_{\text{ph}})$, making our protocol particularly powerful for implementing a sequence of small-angle rotation gates, like Trotter-based circuits. Notably, for $θ_L \lesssim 10^{-5}$, our protocol achieves a two-order-of-magnitude reduction in both the execution time and the error rate of analog rotation gates compared to the standard $T$-gate synthesis using cultivated magic states. Building upon this protocol, we also propose a novel quantum computing architecture designed for early fault-tolerant quantum computers, dubbed ``STAR ver.~3". It employs a refined circuit compilation strategy based on Clifford+$T$+$φ$ gate set, rather than the conventional Clifford+$T$ or Clifford+$φ$ gate sets. We establish a theoretical bound on the feasible circuit size on this architecture and illustrate its capabilities by analyzing the spacetime costs for simulating the dynamics of quantum many-body systems. Specifically, we demonstrate that our architecture can simulate biologically-relevant molecules or lattice models at scales beyond the reach of exact classical simulation, with only a few hundred thousand physical qubits, even assuming a realistic error rate of $p_{\text{ph}}=10^{-3}$.

quant-pharXiv:2603.22891•Mar 25, 2026•0 citations

Transversal Architecture for Megaquop-Scale Quantum Simulation with Neutral Atoms

Refaat Ismail, I-Chi Chen, Chen Zhao +6 more

Quantum computing experiments have made remarkable progress in demonstrating key components of error-corrected quantum computing, a prerequisite for scalable quantum computation. While we anticipate the near-term arrival of early fault-tolerant quantum hardware capable of a million reliable quantum operations, the cost of preparing low-noise “magic resource states,” which are necessary for performing universal quantum computation, presents a formidable challenge. The recently proposed partially fault-tolerant architecture based on a space-time efficient analog rotation (STAR) approach attempts to address this challenge by using postselection to prepare low-noise, arbitrary small-angle magic states. Its proposed physical implementation, however, assumes fixed qubit connectivity, resulting in implementation costs closer to leading fully fault-tolerant approaches. In this work, we propose the transversal STAR architecture and co-design it with neutral-atom quantum hardware, deriving explicit and significant savings in logical layout, time, and space overhead. Through detailed circuit-level simulations, we derive the logical noise model for surface-code-based transversal STAR gadgets and verify their composability. At its limit, the transversal STAR architecture with neutral atoms can efficiently simulate local Hamiltonians with a total simulation volume exceeding 600, defined as the product of the number of logical qubits and Hamiltonian evolution timescales. Achieving this limit would require approximately 10 000 physical qubits at a physical error rate of 10 − 3 . This is equivalent to a fully fault-tolerant computation requiring over 10 6 – 10 7 T gates and a potential > 100 × saving on space-time volume for equivalent simulation over current, state-of-the-art protocols. Finally, we extend the transversal STAR architecture to high-rate quantum low-density parity-check codes, demonstrating how a limited set of highly parallel transversal Clifford gates and generalized small-angle magic injection can be utilized for effective quantum simulation. We anticipate that the co-designed transversal STAR architecture could substantially reduce the physical resources necessary for early fault-tolerant quantum simulation at the megaquop scale.

arXiv:2509.18294•PRX Quantum•Apr 13, 2026•0 citations

End-to-End Optimization of Partial Fault Tolerance in Neutral-Atom Arrays

Stefano Veroni, Aydin Deger, Andrew J. Daley

Fault-tolerant (FT) quantum computation offers a pathway to quantum advantage, but its realization is hindered by its significant overhead. The partially FT "STAR" architecture reduces the cost of universal computation at the price of relaxing FT requirements for non-Clifford operations, increasing exposure to hardware noise. Therefore, maximizing its performance and applicability demands careful co-design with the underlying hardware. In this work we investigate the co-design of the STAR architecture with neutral-atom platforms, connecting the underlying atomic physics to logical error modeling and application-level performance. At the physical level, we identify a favorable noise bias in $^{171}\mathrm{Yb}$ Rydberg gates, and show how it can be enhanced through error-selective pulse optimization. At the logical level, we identify an intrinsic error suppression mechanism, yielding vanishing logical coherent noise in leading order. Detailed circuit-level simulations of surface code implementations show more than an order of magnitude reduction in logical error relative to previous estimates. As a concrete target application, we focus on the Fermi-Hubbard model with periodic boundaries, for which we design a simulation circuit particularly suited to early implementations. We quantify the resource tradeoff of partially and fully FT approaches to gate synthesis, with the former showing approximately an order of magnitude reduction in state-injection depth, and an even larger reduction in Clifford resources. Comparing with classical and fully FT approaches, we identify regimes where partial fault tolerance provides both lower overheads and lower error rates. In our estimates, this is accessible with moderate error rates $p\sim 10^{-3}$ and a few thousand qubits, underlining that for these types of problems, partial FT approaches provide a compelling pathway to early quantum advantage.

quant-pharXiv:2610.26471•Oct 20, 2026•0 citations

Partially Fault-Tolerant Quantum Computation for Megaquop Applications

Ming-Zhi Chung, Ali H. Z. Kavaki, Artur Scherer +14 more

Partially fault-tolerant quantum computing (FTQC) has recently emerged as a promising approach for the execution of megaquop-scale circuits with millions of logical operations. In this work, we demonstrate the strengths and the limitations of this approach by conducting quantum resource estimation (QRE) of the space--time-efficient analog rotation (STAR) architecture using realistic hardware specifications for superconducting processors, and compare it against the QRE of the full FTQC architecture. We show how the performance of the STAR architecture's protocols is affected by hardware improvements. We also reduce the space requirements for partial FTQC by developing a procedure leveraging code growth to decrease the size of a factory producing analog rotation states. Our results reveal a non-trivial dependence of the optimal pre-growth code distance on the rotation angle with respect to post-growth infidelity. Further, we analyze space--time trade-offs between the factory size and the error-mitigation overhead, and observe that in an application-agnostic setting, there is a Goldilocks zone for circuits in the regime of roughly $10^5$--$10^6$ small-angle rotation gates. We show that quantum simulation of 2D Fermi--Hubbard model systems is a particularly well-suited application for the STAR architecture, requiring only hundreds of thousands of physical qubits and runtimes on the order of minutes for modest system sizes. Due to its favourable algorithmic scaling to larger system sizes, utility-scale simulation of the 2D Fermi--Hubbard model could potentially be attained using partial FTQC.

quant-pharXiv:2603.13093•Mar 16, 2026•0 citations

Single-shot magic state factories for quantum LDPC codes

Varun Menon, Rohan Mehta, Andi Gu +8 more

Quantum low-density parity-check (qLDPC) codes can substantially reduce the qubit overhead of fault-tolerant quantum computation, but any useful architecture based on such codes also requires an efficient mechanism to implement non-Clifford gates in a fault-tolerant manner. We introduce a space-time-efficient magic state factory for high-rate qLDPC codes by combining the transversal non-Clifford gates of recently developed tricycle codes with single-shot four-dimensional balanced product quadcycle codes. The key ingredient is an efficient "escape" mechanism that teleports postselected logical magic states from tricycle codes to larger distance quadcycle codes. Under a standard circuit-level noise model at physical error rate $10^{-3}$, our factories produce $\mathrm{CCZ}$ states at logical error rates as low as $10^{-9}$ with 10-40 times lower space-time cost than state-of-the-art magic state generation methods. The resulting states are directly encoded in high-rate blocks suitable for computation. We identify the quadcycle codes by an AI-assisted search and show that they can serve as excellent memories capable of single-shot error correction. Finally, we present a concrete implementation of the entire factory with highly efficient atom transport on reconfigurable neutral-atom quantum computers. Together, these results provide an end-to-end, practical protocol for producing and utilizing high-fidelity magic states within a high-rate qLDPC architecture, with the lowest space-time cost to date.

quant-pharXiv:2610.10731•Oct 9, 2026•0 citations

Routing Codes: High-Rate Quantum LDPC Codes with Short, Parallel Non-Local Connectivity

Jiaxuan Zhang, Zhao-Yun Chen, Peng Duan +6 more

Quantum low-density parity-check (qLDPC) codes are promising candidates for realizing large-scale fault-tolerant quantum computing. Although many codes with favorable theoretical parameters have been developed, their practical adoption must take hardware implementability into account. For mainstream quantum platforms such as superconductors and neutral atoms, the connectivity, the length of non-local couplings, and the complexity of wiring or atom rearrangement are key factors that dictate the difficulty of hardware realization. Here, we propose a new family of qLDPC codes, termed routing codes. Within this family, we find explicit instances whose encoding rates are competitive to those of bivariate bicycle (BB) codes, while systematically reducing qubit connectivity, shortening the length of non-local couplings, and, crucially, making all non-local couplings mutually parallel. This parallelism translates into quantifiable benefits, substantially reducing wiring crossings in superconducting multi-layer architectures and simplifying the scheduling of atom movement in neutral-atom arrays. The weight-7 routing codes maintain a high threshold of 0.7\% and reduce the physical qubit overhead by approximately a factor of 8, compared to surface codes achieving a same logical error rate. Further increasing the weight to 11 yields a [[200, 24, 14]] and [[200, 16, 17]] codes with an encoding rate over 23 times that of the surface code, at the cost of a higher logical error rate. These results establish routing codes as a hardware-centric qLDPC family that bridges the gap between theoretical optimality and near-term physical feasibility.

quant-pharXiv:2606.25330•Jun 25, 2026•0 citations
Fault-tolerant quantum simulation is approaching a phase where encoding overhead, logical Clifford operations, magic-state preparation, and rotation synthesis must be optimized together for efficient implementation. Space-Time efficient Analog Rotation (STAR) architectures reduce two of these costs by preparing small-angle rotation magic states directly, and the transversal STAR variant further lowers the Clifford overhead. Existing concrete implementations, however, largely inherit the low O(1/d2)O(1/d^2)O(1/d2) encoding rate of the surface code, while high-rate codes have not yet been integrated into comparably explicit architectures. Here, we introduce a high-rate STAR architecture for local lattice Hamiltonian simulation based on a symmetry-driven co-design of the algorithm, QEC code, and neutral-atom hardware. Translation symmetries of the target lattice determine the choice of bicycle chain codes, a tunable family of self-dual bivariate bicycle codes that natively implement Clifford gates required for lattice simulation. Disjoint logical representatives allow STAR injections to be performed in parallel on all kkk logical qubits in a code block, amortizing resource state preparation and enabling practical post-selection rates. On neutral-atom platform, the same translation symmetry compiles the key logical operations into low-depth, hardware-native acousto-optic-deflector shifts. End-to-end estimates show that an 8×88 \times 88×8 transverse-field Ising simulation to T∗≈8(zJ)−1T^* \approx 8 (zJ)^{-1}T∗≈8(zJ)−1 requires 224022402240 physical qubits and ∼200\sim 200∼200 s per shot, a ∼5.5×\sim 5.5\times∼5.5× space reduction relative to a surface code STAR baseline at comparable speed; for Fermi-Hubbard dynamics to T∗≈4(zt)−1T^* \approx 4 (zt)^{-1}T∗≈4(zt)−1, the corresponding estimates are ∼6300\sim 6300∼6300 physical qubits and ∼200\sim 200∼200 s per shot. These results provide a concrete route toward early fault-tolerant quantum simulation with high-rate codes.
We introduce STAR-magic mutation, an efficient protocol for implementing logical rotation gates on early fault-tolerant quantum computers. This protocol judiciously combines two of the latest state preparation protocols: transversal multi-rotation protocol and magic state cultivation. It achieves a logical rotation gate with a favorable error scaling of O(θL2(1−Θ(1/d))pph)\mathcal{O}(θ_L^{2(1-Θ(1/d))}p_{\text{ph}})O(θL2(1−Θ(1/d))​pph​), while requiring only the ancillary space of a single surface code patch. Here, θLθ_LθL​ is the logical rotation angle, pphp_{\text{ph}}pph​ is the physical error rate, and ddd is the code distance. This scaling marks a significant improvement over the previous state-of-the-art, O(θLpph)\mathcal{O}(θ_L p_{\text{ph}})O(θL​pph​), making our protocol particularly powerful for implementing a sequence of small-angle rotation gates, like Trotter-based circuits. Notably, for θL≲10−5θ_L \lesssim 10^{-5}θL​≲10−5, our protocol achieves a two-order-of-magnitude reduction in both the execution time and the error rate of analog rotation gates compared to the standard TTT-gate synthesis using cultivated magic states. Building upon this protocol, we also propose a novel quantum computing architecture designed for early fault-tolerant quantum computers, dubbed ``STAR ver.~3". It employs a refined circuit compilation strategy based on Clifford+TTT+φφφ gate set, rather than the conventional Clifford+TTT or Clifford+φφφ gate sets. We establish a theoretical bound on the feasible circuit size on this architecture and illustrate its capabilities by analyzing the spacetime costs for simulating the dynamics of quantum many-body systems. Specifically, we demonstrate that our architecture can simulate biologically-relevant molecules or lattice models at scales beyond the reach of exact classical simulation, with only a few hundred thousand physical qubits, even assuming a realistic error rate of pph=10−3p_{\text{ph}}=10^{-3}pph​=10−3.
Quantum computing experiments have made remarkable progress in demonstrating key components of error-corrected quantum computing, a prerequisite for scalable quantum computation. While we anticipate the near-term arrival of early fault-tolerant quantum hardware capable of a million reliable quantum operations, the cost of preparing low-noise “magic resource states,” which are necessary for performing universal quantum computation, presents a formidable challenge. The recently proposed partially fault-tolerant architecture based on a space-time efficient analog rotation (STAR) approach attempts to address this challenge by using postselection to prepare low-noise, arbitrary small-angle magic states. Its proposed physical implementation, however, assumes fixed qubit connectivity, resulting in implementation costs closer to leading fully fault-tolerant approaches. In this work, we propose the transversal STAR architecture and co-design it with neutral-atom quantum hardware, deriving explicit and significant savings in logical layout, time, and space overhead. Through detailed circuit-level simulations, we derive the logical noise model for surface-code-based transversal STAR gadgets and verify their composability. At its limit, the transversal STAR architecture with neutral atoms can efficiently simulate local Hamiltonians with a total simulation volume exceeding 600, defined as the product of the number of logical qubits and Hamiltonian evolution timescales. Achieving this limit would require approximately 10 000 physical qubits at a physical error rate of 10 − 3 . This is equivalent to a fully fault-tolerant computation requiring over 10 6 – 10 7 T gates and a potential > 100 × saving on space-time volume for equivalent simulation over current, state-of-the-art protocols. Finally, we extend the transversal STAR architecture to high-rate quantum low-density parity-check codes, demonstrating how a limited set of highly parallel transversal Clifford gates and generalized small-angle magic injection can be utilized for effective quantum simulation. We anticipate that the co-designed transversal STAR architecture could substantially reduce the physical resources necessary for early fault-tolerant quantum simulation at the megaquop scale.
Fault-tolerant (FT) quantum computation offers a pathway to quantum advantage, but its realization is hindered by its significant overhead. The partially FT "STAR" architecture reduces the cost of universal computation at the price of relaxing FT requirements for non-Clifford operations, increasing exposure to hardware noise. Therefore, maximizing its performance and applicability demands careful co-design with the underlying hardware. In this work we investigate the co-design of the STAR architecture with neutral-atom platforms, connecting the underlying atomic physics to logical error modeling and application-level performance. At the physical level, we identify a favorable noise bias in 171Yb^{171}\mathrm{Yb}171Yb Rydberg gates, and show how it can be enhanced through error-selective pulse optimization. At the logical level, we identify an intrinsic error suppression mechanism, yielding vanishing logical coherent noise in leading order. Detailed circuit-level simulations of surface code implementations show more than an order of magnitude reduction in logical error relative to previous estimates. As a concrete target application, we focus on the Fermi-Hubbard model with periodic boundaries, for which we design a simulation circuit particularly suited to early implementations. We quantify the resource tradeoff of partially and fully FT approaches to gate synthesis, with the former showing approximately an order of magnitude reduction in state-injection depth, and an even larger reduction in Clifford resources. Comparing with classical and fully FT approaches, we identify regimes where partial fault tolerance provides both lower overheads and lower error rates. In our estimates, this is accessible with moderate error rates p∼10−3p\sim 10^{-3}p∼10−3 and a few thousand qubits, underlining that for these types of problems, partial FT approaches provide a compelling pathway to early quantum advantage.
Partially fault-tolerant quantum computing (FTQC) has recently emerged as a promising approach for the execution of megaquop-scale circuits with millions of logical operations. In this work, we demonstrate the strengths and the limitations of this approach by conducting quantum resource estimation (QRE) of the space--time-efficient analog rotation (STAR) architecture using realistic hardware specifications for superconducting processors, and compare it against the QRE of the full FTQC architecture. We show how the performance of the STAR architecture's protocols is affected by hardware improvements. We also reduce the space requirements for partial FTQC by developing a procedure leveraging code growth to decrease the size of a factory producing analog rotation states. Our results reveal a non-trivial dependence of the optimal pre-growth code distance on the rotation angle with respect to post-growth infidelity. Further, we analyze space--time trade-offs between the factory size and the error-mitigation overhead, and observe that in an application-agnostic setting, there is a Goldilocks zone for circuits in the regime of roughly 10510^5105--10610^6106 small-angle rotation gates. We show that quantum simulation of 2D Fermi--Hubbard model systems is a particularly well-suited application for the STAR architecture, requiring only hundreds of thousands of physical qubits and runtimes on the order of minutes for modest system sizes. Due to its favourable algorithmic scaling to larger system sizes, utility-scale simulation of the 2D Fermi--Hubbard model could potentially be attained using partial FTQC.
Quantum low-density parity-check (qLDPC) codes can substantially reduce the qubit overhead of fault-tolerant quantum computation, but any useful architecture based on such codes also requires an efficient mechanism to implement non-Clifford gates in a fault-tolerant manner. We introduce a space-time-efficient magic state factory for high-rate qLDPC codes by combining the transversal non-Clifford gates of recently developed tricycle codes with single-shot four-dimensional balanced product quadcycle codes. The key ingredient is an efficient "escape" mechanism that teleports postselected logical magic states from tricycle codes to larger distance quadcycle codes. Under a standard circuit-level noise model at physical error rate 10−310^{-3}10−3, our factories produce CCZ\mathrm{CCZ}CCZ states at logical error rates as low as 10−910^{-9}10−9 with 10-40 times lower space-time cost than state-of-the-art magic state generation methods. The resulting states are directly encoded in high-rate blocks suitable for computation. We identify the quadcycle codes by an AI-assisted search and show that they can serve as excellent memories capable of single-shot error correction. Finally, we present a concrete implementation of the entire factory with highly efficient atom transport on reconfigurable neutral-atom quantum computers. Together, these results provide an end-to-end, practical protocol for producing and utilizing high-fidelity magic states within a high-rate qLDPC architecture, with the lowest space-time cost to date.
Quantum low-density parity-check (qLDPC) codes are promising candidates for realizing large-scale fault-tolerant quantum computing. Although many codes with favorable theoretical parameters have been developed, their practical adoption must take hardware implementability into account. For mainstream quantum platforms such as superconductors and neutral atoms, the connectivity, the length of non-local couplings, and the complexity of wiring or atom rearrangement are key factors that dictate the difficulty of hardware realization. Here, we propose a new family of qLDPC codes, termed routing codes. Within this family, we find explicit instances whose encoding rates are competitive to those of bivariate bicycle (BB) codes, while systematically reducing qubit connectivity, shortening the length of non-local couplings, and, crucially, making all non-local couplings mutually parallel. This parallelism translates into quantifiable benefits, substantially reducing wiring crossings in superconducting multi-layer architectures and simplifying the scheduling of atom movement in neutral-atom arrays. The weight-7 routing codes maintain a high threshold of 0.7\% and reduce the physical qubit overhead by approximately a factor of 8, compared to surface codes achieving a same logical error rate. Further increasing the weight to 11 yields a [[200, 24, 14]] and [[200, 16, 17]] codes with an encoding rate over 23 times that of the surface code, at the cost of a higher logical error rate. These results establish routing codes as a hardware-centric qLDPC family that bridges the gap between theoretical optimality and near-term physical feasibility.