Quantum computing experiments have made remarkable progress in demonstrating key components of error-corrected quantum computing, a prerequisite for scalable quantum computation. While we anticipate the near-term arrival of early fault-tolerant quantum hardware capable of a million reliable quantum operations, the cost of preparing low-noise “magic resource states,” which are necessary for performing universal quantum computation, presents a formidable challenge. The recently proposed partially fault-tolerant architecture based on a space-time efficient analog rotation (STAR) approach attempts to address this challenge by using postselection to prepare low-noise, arbitrary small-angle magic states. Its proposed physical implementation, however, assumes fixed qubit connectivity, resulting in implementation costs closer to leading fully fault-tolerant approaches. In this work, we propose the transversal STAR architecture and co-design it with neutral-atom quantum hardware, deriving explicit and significant savings in logical layout, time, and space overhead. Through detailed circuit-level simulations, we derive the logical noise model for surface-code-based transversal STAR gadgets and verify their composability. At its limit, the transversal STAR architecture with neutral atoms can efficiently simulate local Hamiltonians with a total simulation volume exceeding 600, defined as the product of the number of logical qubits and Hamiltonian evolution timescales. Achieving this limit would require approximately 10 000 physical qubits at a physical error rate of 10 − 3 . This is equivalent to a fully fault-tolerant computation requiring over 10 6 – 10 7 T gates and a potential > 100 × saving on space-time volume for equivalent simulation over current, state-of-the-art protocols. Finally, we extend the transversal STAR architecture to high-rate quantum low-density parity-check codes, demonstrating how a limited set of highly parallel transversal Clifford gates and generalized small-angle magic injection can be utilized for effective quantum simulation. We anticipate that the co-designed transversal STAR architecture could substantially reduce the physical resources necessary for early fault-tolerant quantum simulation at the megaquop scale.
Fault-tolerant quantum simulation is approaching a phase where encoding overhead, logical Clifford operations, magic-state preparation, and rotation synthesis must be optimized together for efficient implementation. Space-Time efficient Analog Rotation (STAR) architectures reduce two of these costs by preparing small-angle rotation magic states directly, and the transversal STAR variant further lowers the Clifford overhead. Existing concrete implementations, however, largely inherit the low
O(1/d2) encoding rate of the surface code, while high-rate codes have not yet been integrated into comparably explicit architectures. Here, we introduce a high-rate STAR architecture for local lattice Hamiltonian simulation based on a symmetry-driven co-design of the algorithm, QEC code, and neutral-atom hardware. Translation symmetries of the target lattice determine the choice of bicycle chain codes, a tunable family of self-dual bivariate bicycle codes that natively implement Clifford gates required for lattice simulation. Disjoint logical representatives allow STAR injections to be performed in parallel on all
k logical qubits in a code block, amortizing resource state preparation and enabling practical post-selection rates. On neutral-atom platform, the same translation symmetry compiles the key logical operations into low-depth, hardware-native acousto-optic-deflector shifts. End-to-end estimates show that an
8×8 transverse-field Ising simulation to
T∗≈8(zJ)−1 requires
2240 physical qubits and
∼200 s per shot, a
∼5.5× space reduction relative to a surface code STAR baseline at comparable speed; for Fermi-Hubbard dynamics to
T∗≈4(zt)−1, the corresponding estimates are
∼6300 physical qubits and
∼200 s per shot. These results provide a concrete route toward early fault-tolerant quantum simulation with high-rate codes.
Fault-tolerant (FT) quantum computation offers a pathway to quantum advantage, but its realization is hindered by its significant overhead. The partially FT "STAR" architecture reduces the cost of universal computation at the price of relaxing FT requirements for non-Clifford operations, increasing exposure to hardware noise. Therefore, maximizing its performance and applicability demands careful co-design with the underlying hardware. In this work we investigate the co-design of the STAR architecture with neutral-atom platforms, connecting the underlying atomic physics to logical error modeling and application-level performance. At the physical level, we identify a favorable noise bias in
171Yb Rydberg gates, and show how it can be enhanced through error-selective pulse optimization. At the logical level, we identify an intrinsic error suppression mechanism, yielding vanishing logical coherent noise in leading order. Detailed circuit-level simulations of surface code implementations show more than an order of magnitude reduction in logical error relative to previous estimates. As a concrete target application, we focus on the Fermi-Hubbard model with periodic boundaries, for which we design a simulation circuit particularly suited to early implementations. We quantify the resource tradeoff of partially and fully FT approaches to gate synthesis, with the former showing approximately an order of magnitude reduction in state-injection depth, and an even larger reduction in Clifford resources. Comparing with classical and fully FT approaches, we identify regimes where partial fault tolerance provides both lower overheads and lower error rates. In our estimates, this is accessible with moderate error rates
p∼10−3 and a few thousand qubits, underlining that for these types of problems, partial FT approaches provide a compelling pathway to early quantum advantage.
We introduce STAR-magic mutation, an efficient protocol for implementing logical rotation gates on early fault-tolerant quantum computers. This protocol judiciously combines two of the latest state preparation protocols: transversal multi-rotation protocol and magic state cultivation. It achieves a logical rotation gate with a favorable error scaling of
O(θL2(1−Θ(1/d))pph), while requiring only the ancillary space of a single surface code patch. Here,
θL is the logical rotation angle,
pph is the physical error rate, and
d is the code distance. This scaling marks a significant improvement over the previous state-of-the-art,
O(θLpph), making our protocol particularly powerful for implementing a sequence of small-angle rotation gates, like Trotter-based circuits. Notably, for
θL≲10−5, our protocol achieves a two-order-of-magnitude reduction in both the execution time and the error rate of analog rotation gates compared to the standard
T-gate synthesis using cultivated magic states. Building upon this protocol, we also propose a novel quantum computing architecture designed for early fault-tolerant quantum computers, dubbed ``STAR ver.~3". It employs a refined circuit compilation strategy based on Clifford+
T+
φ gate set, rather than the conventional Clifford+
T or Clifford+
φ gate sets. We establish a theoretical bound on the feasible circuit size on this architecture and illustrate its capabilities by analyzing the spacetime costs for simulating the dynamics of quantum many-body systems. Specifically, we demonstrate that our architecture can simulate biologically-relevant molecules or lattice models at scales beyond the reach of exact classical simulation, with only a few hundred thousand physical qubits, even assuming a realistic error rate of
pph=10−3.
Partially fault-tolerant quantum computing (FTQC) has recently emerged as a promising approach for the execution of megaquop-scale circuits with millions of logical operations. In this work, we demonstrate the strengths and the limitations of this approach by conducting quantum resource estimation (QRE) of the space--time-efficient analog rotation (STAR) architecture using realistic hardware specifications for superconducting processors, and compare it against the QRE of the full FTQC architecture. We show how the performance of the STAR architecture's protocols is affected by hardware improvements. We also reduce the space requirements for partial FTQC by developing a procedure leveraging code growth to decrease the size of a factory producing analog rotation states. Our results reveal a non-trivial dependence of the optimal pre-growth code distance on the rotation angle with respect to post-growth infidelity. Further, we analyze space--time trade-offs between the factory size and the error-mitigation overhead, and observe that in an application-agnostic setting, there is a Goldilocks zone for circuits in the regime of roughly
105--
106 small-angle rotation gates. We show that quantum simulation of 2D Fermi--Hubbard model systems is a particularly well-suited application for the STAR architecture, requiring only hundreds of thousands of physical qubits and runtimes on the order of minutes for modest system sizes. Due to its favourable algorithmic scaling to larger system sizes, utility-scale simulation of the 2D Fermi--Hubbard model could potentially be attained using partial FTQC.
Recent advancements in neutral atom platforms have enabled exploration of early fault-tolerant (FT) architectures for applications with quantum advantage, such as quantum dynamics simulations. An efficient fault-tolerant architecture has both spatially efficient quantum error correction codes (low qubit overhead), and efficient methodologies (transversal based gates, extractor based gates, etc.) for logical computation, to minimize overall execution time. Achieving the right balance between space and time can be critical for enabling early FT demonstrations of quantum advantage.
In this work, we identify bottlenecks in existing spatially efficient schemes, which tend to be very serial, and do not take advantage of unutilized space. We introduce a teleportation-based scheme that leverages the reconfigurable connectivity of neutral atoms to parallelize logical operations. Our approach achieves up to \textbf{
∼3× speedup} over extractor architectures at no extra space cost and achieves the best spacetime performance among other viable architectures before accounting for external \textit{resource-states}. To rigorously evaluate performance, we construct explicit quantum advantage benchmarks and \textit{simulate} compilation to a fault-tolerant instruction set, including low-level gate scheduling and shuttling patterns, and resource-state nondeterminism. We find that our speedups still apply and report exact space-time cost along with success probabilities, identifying architectures capable of achieving quantum advantage \textbf{with as little as
11,495 atoms and a runtime of
∼15 hours}.
Quantum low-density parity-check (qLDPC) codes offer a promising route to scalable fault-tolerant quantum computing due to their substantially reduced footprint. However, these gains can be diluted at utility scale if we cannot also realize space-time efficient logical operations for relevant quantum applications. We present RASCqL, a reaction-time-limited architecture for space-time efficient complex-instruction-set quantum computation with qLDPC logic. RASCqL supports key algorithmic subroutines such as quantum arithmetic and state preparation directly within co-designed qLDPC codes, achieving
2× to
7× reductions in qubit footprint while maintaining space-time volume comparable to state-of-the-art transversal surface-code architectures. Unlike prior approaches that aim for versatile logical instruction sets for arbitrary circuits, RASCqL adopts an application-tailored code modification that embeds specific complex Clifford transformations useful for common subroutines as virtually implementable operations arising from code automorphisms. RASCqL further leverages parallel physical operations available in reconfigurable neutral-atom arrays to enable fast QEC cycles and high-fidelity transversal operations. At the cost of increased design complexity and specialization, RASCqL can improve end-to-end resource estimates for applications such as factoring and quantum chemistry simulation in both footprint and space-time volume under realistic physical error rates of approximately
2×10−3 to
5×10−4, without requiring additional hardware capabilities. These results demonstrate that qLDPC codes can serve as complex quantum logic units for useful quantum algorithms, extending their practical utility in fault-tolerant quantum computing architectures.