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arXiv:2601.10203 · Quantum Science and Technology

Topology-Aware Block Coordinate Descent for Qubit Frequency Calibration of Superconducting Quantum Processors

Zheng Zhao, Weifeng Zhuang, Yanwu Gu, Peng Qian, Xiao Xiao, Dong E. Liu

quant-phSubmitted Jan 15, 2026• Announced Jan 16, 2026• 0 citations
v1 · Jan 15, 2026v2 · Mar 25, 2026
arXivHTMLPDF

Abstract

Pre-execution calibration is a major bottleneck for operating superconducting quantum processors, and qubit frequency allocation is especially challenging due to crosstalk-coupled objectives. We establish that the widely-used Snake optimizer is mathematically equivalent to Block Coordinate Descent (BCD), providing a rigorous theoretical foundation for this calibration strategy. Building on this formalization, we present a topology-aware block ordering obtained by casting order selection as a Sequence-Dependent Traveling Salesman Problem (SD-TSP) and solving it efficiently with a nearest-neighbor heuristic. The SD-TSP cost reflects how a given block choice expands the reduced-circuit footprint required to evaluate the block-local objective, enabling orders that minimize per-epoch evaluation time. Under local crosstalk/bounded-degree assumptions, the method achieves linear complexity in qubit count per epoch, while retaining calibration quality. We formalize the calibration objective, clarify when reduced experiments are equivalent or approximate to the full objective, and analyze convergence of the resulting inexact BCD with noisy measurements. Simulations on multi-qubit models show that the proposed BCD-NNA ordering attains the same optimization accuracy at markedly lower runtime than graph-based heuristics (BFS, DFS) and random orders, and is robust to measurement noise and tolerant to moderate non-local crosstalk. These results provide a scalable, implementation-ready workflow for frequency calibration on NISQ-era processors.

Journal reference
Quantum Sci. Technol. 11 035023 (2026)
DOI
10.1088/2058-9565/ae6fe6
Comments
17 pages,6 figures

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Pre-execution calibration is a major bottleneck for operating superconducting quantum processors, and qubit frequency allocation is especially challenging due to crosstalk-coupled objectives. We establish that the widely-used Snake optimizer is mathematically equivalent to Block Coordinate Descent (BCD), providing a rigorous theoretical foundation for this calibration strategy. Building on this formalization, we present a topology-aware block ordering obtained by casting order selection as a Sequence-Dependent Traveling Salesman Problem (SD-TSP) and solving it efficiently with a nearest-neighbor heuristic. The SD-TSP cost reflects how a given block choice expands the reduced-circuit footprint required to evaluate the block-local objective, enabling orders that minimize per-epoch evaluation time. Under local crosstalk/bounded-degree assumptions, the method achieves linear complexity in qubit count per epoch, while retaining calibration quality. We formalize the calibration objective, clarify when reduced experiments are equivalent or approximate to the full objective, and analyze convergence of the resulting inexact BCD with noisy measurements. Simulations on multi-qubit models show that the proposed BCD-NNA ordering attains the same optimization accuracy at markedly lower runtime than graph-based heuristics (BFS, DFS) and random orders, and is robust to measurement noise and tolerant to moderate non-local crosstalk. These results provide a scalable, implementation-ready workflow for frequency calibration on NISQ-era processors.
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This study proposes a scalable pre-processing method that incorporates crosstalk effects in quantum devices, with a focus on mitigating measurement errors. Measurement errors are modeled as a transition probability matrix between ideal and noisy distributions. However, the size of this matrix grows exponentially with the number of qubits, posing a major challenge for large systems. To overcome this, we exploit two empirical observations obtained from experiments on an 8-qubit superconducting quantum device: (i) error correlations are strongly influenced by the topology of the qubit connectivity, and (ii) the mitigated observable exhibits locality, with dominant contributions from low-order terms. Based on these features, we introduce an approximation scheme that restricts attention to observables with limited locality and to qubits within a bounded distance on a device graph. Transition probabilities are efficiently estimated using parallel measurements based on a perfect hash family, reducing the required number of measurements from polynomial to quasi-linear in system size. We validate our approach on a 32-qubit device and demonstrate that it achieves a 50 % reduction in error compared to unmitigated data and a 10 % improvement over a conventional method that neglects crosstalk. Our results highlight the potential of topology-aware, locality-preserving error mitigation for enhancing quantum computations on near-term devices.
Frequency crowding, the close spacing of qubit transitions, limits superconducting quantum processors through crosstalk, leakage, and spectator dependent errors. We introduce a Hamiltonian based framework that maps two- and three-body collision mechanisms onto a Max-k-Cut problem on qubit frequency allocation. In order to make larger lattices tractable, we introduce a cluster-stitching protocol that decomposes larger lattices into overlapping subgraphs and reconciles their local frequency assignments into globally consistent configurations. We tested our proposed framework across multiple qubit architectures to suppress dominant collision penalties by revealing a hardware residual crosstalk. We benchmark digitized counterdiabatic QAOA (DC-QAOA), standard QAOA, and simulated annealing. Counterdiabatic terms improve QAOA optimization near steep collision penalties, while simulated annealing achieves the lowest costs on the tested instances. These results indicate that our hardware-aware optimization connects microscopic interaction physics to processor-level frequency planning. These results enable a systematic solver for benchmarking of scalable software hardware co design.
A foundational assumption of quantum error correction theory is that quantum gates can be scaled to large processors without exceeding the error-threshold for fault tolerance. Two major challenges that could become fundamental roadblocks are manufacturing high-performance quantum hardware and engineering a control system that can reach its performance limits. The control challenge of scaling quantum gates from small to large processors without degrading performance often maps to non-convex, high-constraint, and time-dynamic control optimization over an exponentially expanding configuration space. Here we report on a control optimization strategy that can scalably overcome the complexity of such problems. We demonstrate it by choreographing the frequency trajectories of 68 frequency-tunable superconducting qubits to execute single- and two-qubit gates while mitigating computational errors. When combined with a comprehensive model of physical errors across our processor, the strategy suppresses physical error rates by ~3.7× compared with the case of no optimization. Furthermore, it is projected to achieve a similar performance advantage on a distance-23 surface code logical qubit with 1057 physical qubits. Our control optimization strategy solves a generic scaling challenge in a way that can be adapted to a variety of quantum operations, algorithms, and computing architectures.
Quantum algorithms need to be compiled to respect the constraints imposed by quantum processors, which is known as the mapping problem. The mapping procedure will result in an increase of the number of gates and of the circuit latency, decreasing the algorithm’s success rate. It is crucial to minimize mapping overhead, especially for noisy intermediate-scale quantum (NISQ) processors that have relatively short qubit coherence times and high gate error rates. Most of prior mapping algorithms have only considered constraints, such as the primitive gate set and qubit connectivity, but the actual gate duration and the restrictions imposed by the use of shared classical control electronics have not been taken into account. In this article, we present a mapper called Qmap to make quantum circuits executable on scalable processors with the objective of achieving the shortest circuit latency. In particular, we propose an approach to formulate the classical control restrictions as resource constraints in a conventional list scheduler with polynomial complexity. Furthermore, we implement a routing heuristic to cope with the connectivity limitation. This router finds a set of movement operations that minimally extends circuit latency. To analyze the mapping overhead and evaluate the performance of different mappers, we map 56 quantum benchmarks onto a superconducting processor named Surface-17. Compared to a prior mapping strategy that minimizes the number of operations, Qmap can reduce the latency overhead (LtyOH) up to 47.3% and operation overhead up to 28.6%, respectively.
Crosstalk between qubits fundamentally limits the scalability of quantum processors, necessitating physics-based models that can handle the complexity of large qubit arrays. Here, we develop a comprehensive theoretical and experimental framework that captures residual interactions between both adjacent and non-adjacent qubits in fixed-frequency transmon lattices. The model integrates the combined effects of exponential localization in banded capacitance matrices, suppression of virtual couplings through detuning products across intermediate modes, and evanescent decay of below-cutoff electromagnetic fields, yielding predictive scaling relations for coupling strength as a function of spatial separation and spectral detuning. Experimental characterization of a 4×44 \times 44×4 superconducting-qubit lattice with inductive shunt pillars reveals exponential spatial decay and frequency-dependent suppression consistent with theoretical predictions, achieving quantitative agreement for all nearest-neighbor couplings across the \qtyrange[range-phrase = --, range-units = single]{4}{6}{\giga\hertz} operating range. Our results show that standard dispersive Hamiltonian approximations systematically overestimate long-range coupling when spatial and spectral dependencies are neglected; these errors propagate into circuit simulation and design strategies. Our framework provides design guidance for crosstalk mitigation in larger-scale quantum processors under realistic fabrication constraints, addressing a bottleneck in scalability.