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arXiv:2511.19432

Robotic chip-scale nanofabrication for superior consistency

Felix M. Mayor, Wenyan Guan, Erik Szakiel, Amir H. Safavi-Naeini, Samuel Gyger

physics.app-phcond-mat.mes-hallquant-phSubmitted Nov 24, 2025• Announced Nov 25, 2025
arXivHTMLPDF

Abstract

Unlike the rigid, high-volume automation found in industry, academic research requires process flexibility that has historically relied on variable manual operations. This hinders the fabrication of advanced, complex devices. We propose to address this gap by automating these low-volume, high-stakes tasks using a robotic arm to improve process control and consistency. As a proof of concept, we deploy this system for the resist development of Josephson junction devices. A statistical comparison of the process repeatability shows the robotic process achieves a resistance spread across chips close to 2%, a significant improvement over the ~7% spread observed from human operators, validating robotics as a solution to eliminate operator-dependent variability and a path towards industrial-level consistency in a research setting.

Journal reference
Appl. Phys. Lett. 128, 144101 (2026)
DOI
10.1063/5.0313577
Comments
5 pages, 3 figures

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Unlike the rigid, high-volume automation found in industry, academic research requires process flexibility that has historically relied on variable manual operations. This hinders the fabrication of advanced, complex devices. We propose to address this gap by automating these low-volume, high-stakes tasks using a robotic arm to improve process control and consistency. As a proof of concept, we deploy this system for the resist development of Josephson junction devices. A statistical comparison of the process repeatability shows the robotic process achieves a resistance spread across chips close to 2%, a significant improvement over the ~7% spread observed from human operators, validating robotics as a solution to eliminate operator-dependent variability and a path towards industrial-level consistency in a research setting.
Variability in Josephson junction area and resistance remains a central challenge in scaling fixed-frequency superconducting qubit architectures, where resistance fluctuations translate into qubit-frequency dispersion and potential frequency collisions. Here, we present a fabrication strategy that combines large-area process control on 200 mm wafers with chip-level electrical fine-tuning to improve junction-resistance repeatability. Within a central 80 × 80 mm 2 field on 200 mm wafers, the Manhattan-style aluminum junction process yielded relative standard deviations of 5.1–5.2% in junction area (RSD A ) and 5.8–7.2% in room-temperature resistance (RSD R ). Alternating-bias assisted annealing (ABAA) further reduced chip-level RSD R to 1.3% in a chip with all 20 junctions tuned and to 1.7% for 16 tuned junctions in a cryogenically characterized 20-qubit chip. In a cross-chip comparison, the coherence distributions of the ABAA-treated chip and the untreated reference chip overlapped. These results show that large-area feed-forward correction and post-fabrication tuning can improve junction-parameter repeatability in fixed-frequency superconducting circuits.
The Josephson junction (JJ) is the fundamental nonlinear building block of superconducting quantum technologies. Its macroscopic quantum tunneling physics underpins superconducting quantum computing, sensing, and communication, but scaling these platforms to utility-scale architectures places increasingly stringent demands on junction materials, interfaces, and fabrication. Practical quantum computing requires high reproducibility, low power consumption, tunability, a small device footprint, and resilience to noise and defects. This review surveys how advances in materials science, device characterization, and nanofabrication are addressing these challenges and redefining the figures of merit for next-generation JJs. This review also examines the evolution of fabrication strategies, from conventional multi-angle evaporation to foundry-compatible superconducting processes and the integration of emerging junction materials. Progress along these directions will determine how rapidly JJs move from laboratory-scale components to the foundation of industrial-scale quantum processors.
We introduce a simplified fabrication technique for Josephson junctions and demonstrate superconducting Xmon qubits with T1 relaxation times averaging above 50 μs (Q>1.5×106). Current shadow-evaporation techniques for aluminum-based Josephson junctions require a separate lithography step to deposit a patch that makes a galvanic, superconducting connection between the junction electrodes and the circuit wiring layer. The patch connection eliminates parasitic junctions, which otherwise contribute significantly to dielectric loss. In our patch-integrated cross-type junction technique, we use one lithography step and one vacuum cycle to evaporate both the junction electrodes and the patch. This eliminates a key bottleneck in manufacturing superconducting qubits by reducing the fabrication time and cost. In a study of more than 3600 junctions, we show an average resistance variation of 3.7% on a wafer that contains forty 0.5×0.5-cm2 chips, with junction areas ranging between 0.01 and 0.16 μm2. The average on-chip spread in resistance is 2.7%, with 20 chips varying between 1.4% and 2%. For the junction sizes used for transmon qubits, we deduce a wafer-level transition-frequency variation of 1.7%–2.5%. We show that 60%–70% of this variation is attributed to junction-area fluctuations, while the rest is caused by tunnel-junction inhomogeneity. Such high frequency predictability is a requirement for scaling-up the number of qubits in a quantum computer.
The development of useful quantum technologies will heavily rely on assembling many sub-systems that exhibit quantum properties. These systems do not spontaneously assemble themselves into useable quantum machines: they rely on advanced fabrication techniques at micro- and nanometre scales. Examples of such techniques include the fabrication of electrodes and waveguides for trapped ions, of Josephson junctions and microwave chips for superconducting circuits, of electrodes for the control of quantum dots or the fabrication of low-disorder semi-conductors for the operation of Majorana Zero Modes.
Ongoing research at SUNY Polytechnic Institute to enable large scale fabrication of quantum devices with tightly controlled performance characteristics will be presented. Josephson junctions and transmon qubits patterned with 193 nm lithography will be used to illustrate how advanced process tools can control critical dimensions of devices, necessary for building larger ensembles of qubits. Advances in the CMOS industry enable superior surface roughness and interface quality to be achieved across the entire 300mm wafer – some examples will be presented. The integration of photonic circuits (waveguides and on-chip cryogenic IR emitters) with superconducting Josephson junctions to enable large-scale neuromorphic computing structures in the near future will be discussed. Ongoing work on developing materials and processes for UV-transparent photonic circuits at 300mm will be presented – such chips could be useful as part of the interface to trapped ion qubits. The talk will wrap up with a discussion of the synergies in technology development, and functionality integration that can be achieved using an advanced fabrication facility.
Abstract Josephson superconducting qubits and parametric amplifiers are prominent examples of superconducting quantum circuits that have shown rapid progress in recent years. As such devices become more complex, the requirements for reproducibility of their electrical properties across a chip are being tightened. Critical current of the Josephson junction Ic is the essential electrical parameter in a chip. So, its variation is to be minimized. According to the Ambegaokar–Baratoff formula, critical current is related to normal-state resistance, which can be measured at room temperature. In this study, we focused on the dominant source of non-uniformity for the Josephson junction critical current–junction area variation. We optimized Josephson junction fabrication process and demonstrated resistance variation of 9.8–4.4% and 4.8–2.3% across 22 × 22 mm2 and 5 × 10 mm2 chip areas, respectively. For a wide range of junction areas from 0.008 to 0.12 μm2, we ensure a small linewidth standard deviation of 4 nm measured over 4500 junctions with linear dimensions from 80 to 680 nm. We found that the dominate source of junction area variation limiting Ic{\mathrm{I}}_{\mathrm{c}}Ic​ I c reproducibility is the imperfection of the evaporation system. The developed fabrication process was tested on superconducting highly coherent transmon qubits (T1 > 100 μs) and a nonlinear asymmetric inductive element parametric amplifier.