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arXiv:2511.13256 · Physics Letters A

Depth optimization of CNOT ladder circuits

Spyros Tserkis, Muhammad Umer, Dimitris G. Angelakis

quant-phSubmitted Nov 17, 2025• Announced Nov 18, 2025• 0 citations• Revised Mar 23, 2026 (v2)
v1 · Nov 17, 2025v2 · Mar 23, 2026
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Abstract

The increasing depth of quantum circuits presents a major limitation for the execution of quantum algorithms, as the limited coherence time of physical qubits leads to noise that manifests as errors during computation. In this work, we focus on CNOT ladder circuits, which find applications in several quantum computing tasks, including the preparation of GHZ states, the implementation of fan-out and long-range CNOT gates, fermionic simulations, and the construction of ansatz circuits for variational quantum computing. The linearly increasing depth of a CNOT ladder circuit can be exchanged for constant CNOT depth at the expense of wider circuits that rely on mid-circuit measurements and classically controlled operations. Our error analysis shows that the choice between these two constructions depends on the relative difference between CNOT and idling error rates. Overall, the technique developed in this work enables low-depth implementations of circuits that are ubiquitous in quantum computing algorithms.

Comments
8 pages, 5 figures

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The increasing depth of quantum circuits presents a major limitation for the execution of quantum algorithms, as the limited coherence time of physical qubits leads to noise that manifests as errors during computation. In this work, we focus on CNOT ladder circuits, which find applications in several quantum computing tasks, including the preparation of GHZ states, the implementation of fan-out and long-range CNOT gates, fermionic simulations, and the construction of ansatz circuits for variational quantum computing. The linearly increasing depth of a CNOT ladder circuit can be exchanged for constant CNOT depth at the expense of wider circuits that rely on mid-circuit measurements and classically controlled operations. Our error analysis shows that the choice between these two constructions depends on the relative difference between CNOT and idling error rates. Overall, the technique developed in this work enables low-depth implementations of circuits that are ubiquitous in quantum computing algorithms.
The depth of quantum circuits is a critical factor when running them on state-of-the-art quantum devices owing to their limited coherence times. Reducing circuit depth decreases noise in near-term quantum computations and reduces overall computation time. This also benefits fault-tolerant quantum computations. Here, we show how to reduce the depth of quantum subroutines that typically scale linearly with the number of qubits, such as quantum fan-out and long-range CNOT gates, to a constant depth using mid-circuit measurements and feedforward operations, while only requiring a 1D line topology. We compare our protocols with existing ones to highlight their advantages. Additionally, we verify the feasibility by implementing the measurement-based quantum fan-out gate and long-range CNOT gate on real quantum hardware, demonstrating significant improvements over their unitary implementations.
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We focus on the depth optimization of CNOT circuits on hardware with limited connectivity. We adapt the algorithm from Kutin et al. that implements any n -qubit CNOT circuit in depth at most 5n on a Linear Nearest Neighbor architecture. Our proposal is a block version of Kutin et al.’s algorithm that is scalable with the number of interactions available in the hardware: the more interactions we have, the less the depth. We derive better theoretical upper bounds and provide a simple implementation of the algorithm. Overall, we achieve better depth complexity for CNOT circuits on some realistic quantum hardware like a grid or a ladder. For instance, the execution of an n -qubit CNOT circuit on a grid can be done in depth 4n+8 .
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