We focus on the depth optimization of CNOT circuits on hardware with limited connectivity. We adapt the algorithm from Kutin et al. that implements any n -qubit CNOT circuit in depth at most 5n on a Linear Nearest Neighbor architecture. Our proposal is a block version of Kutin et al.’s algorithm that is scalable with the number of interactions available in the hardware: the more interactions we have, the less the depth. We derive better theoretical upper bounds and provide a simple implementation of the algorithm. Overall, we achieve better depth complexity for CNOT circuits on some realistic quantum hardware like a grid or a ladder. For instance, the execution of an n -qubit CNOT circuit on a grid can be done in depth 4n+8 .
We focus on the depth optimization of CNOT circuits on hardware with limited connectivity. We adapt the algorithm from Kutin et al. that implements any n -qubit CNOT circuit in depth at most 5n on a Linear Nearest Neighbor architecture. Our proposal is a block version of Kutin et al.’s algorithm that is scalable with the number of interactions available in the hardware: the more interactions we have, the less the depth. We derive better theoretical upper bounds and provide a simple implementation of the algorithm. Overall, we achieve better depth complexity for CNOT circuits on some realistic quantum hardware like a grid or a ladder. For instance, the execution of an n -qubit CNOT circuit on a grid can be done in depth 4n+8 .
The increasing depth of quantum circuits presents a major limitation for the execution of quantum algorithms, as the limited coherence time of physical qubits leads to noise that manifests as errors during computation. In this work, we focus on CNOT ladder circuits, which find applications in several quantum computing tasks, including the preparation of GHZ states, the implementation of fan-out and long-range CNOT gates, fermionic simulations, and the construction of ansatz circuits for variational quantum computing. The linearly increasing depth of a CNOT ladder circuit can be exchanged for constant CNOT depth at the expense of wider circuits that rely on mid-circuit measurements and classically controlled operations. Our error analysis shows that the choice between these two constructions depends on the relative difference between CNOT and idling error rates. Overall, the technique developed in this work enables low-depth implementations of circuits that are ubiquitous in quantum computing algorithms.
In quantum computing the decoherence time of the qubits determines the computation time available, and this time is very limited when using current hardware. In this article, we minimize the execution time (the depth) for a class of circuits referred to as linear reversible circuits, which has many applications in quantum computing (e.g., stabilizer circuits, “CNOT+T” circuits, etc.). We propose a practical formulation of a divide-and-conquer algorithm that produces quantum circuits that are twice as shallow as those produced by existing algorithms. We improve the theoretical upper bound of the depth in the worst case for some range of qubits. We also propose greedy algorithms based on cost minimization to find more optimal circuits for small or simple operators. Overall, we manage to consistently reduce the total depth of a class of reversible functions, with up to 92% savings in an ancilla-free case and up to 99% when ancillary qubits are available.
A controlled-not (cnot) circuit is the key gadget for entangling qubits in quantum computing systems. However, the qubit connectivity of noisy intermediate-scale quantum (NISQ) devices is constrained by their limited-connectivity architecture. To improve the performance of cnot circuits on NISQ devices, we investigate the optimization of the size/depth of cnot circuits under the limited-connectivity architecture. We present a method that can optimize the size of any n-qubit cnot circuit $O(\frac{{n}^{2}}{log\ensuremath{\delta}})$ on any connected graph with minimum degree $\ensuremath{\delta}$, and prove this bound is optimal for the regular graph. For the near-term sparsely connected structure, we additionally present a method that can optimize the size of any n-qubit cnot circuit to below 2n2. The numerical experiment shows that our method performs better than state-of-the-art results. Specifically, we present an example to illustrate the applicability of our algorithm. For the grid structure, which is commonly used in current quantum devices, we demonstrate that the depth of any n-qubit cnot circuit can be optimized to be linear in n with certain ancillary qubits (ancillas). Experimental results indicate that this method has significant improvements compared with all of the existing methods. We additionally test our algorithms on the five-qubit IBMQ devices, and the experiments show that the measurement results of the optimized circuit with our algorithm are more robust to noise compared with the IBM mapping method.
We propose a versatile method for implementing quantum algorithms that simultaneously minimizes gate count and circuit depth. Central to our approach are Parity Twine chains-CNOT-based building blocks tailored to hardware connectivity. This technique surpasses existing state-of-the-art methods in executing key quantum algorithms, including the Quantum Fourier Transform and the Quantum Approximate Optimization Algorithm, across various quantum hardware architectures such as linear chains, square grids, hexagonal lattices, ladders, and fully connected systems.
CNOT circuit is the key gadget for entangling qubits in quantum computing systems. However, the qubit connectivity of noisy intermediate-scale quantum (NISQ) devices is constrained by their topological structures. To improve the performance of CNOT circuits on NISQ devices, we investigate the optimization of the size/depth of CNOT circuits under topological constraints. We firstly present a method that can optimize the size of any n-qubit CNOT circuit to less than 2n2 on any connected graph, which is optimal for sparsely connected structures. The simulation experiment shows that our method performs better than state-of-the-art results. Specifically, we present two detailed examples to illustrate the applicability of our algorithm. Furthermore, for the future device with a denser structure, we give a better optimization method that achieves O(n2/logδ) size on a graph with the minimum degree δ, which is optimal on the regular graph. Secondly, for the grid structure, which is commonly used in current quantum devices, we demonstrate that the depth of any n-qubit CNOT circuit can be optimized to be linear in n with certain ancillary qubits (ancillas). Our experimental results indicate this method has significant improvements compared with all of the existing methods. We further implement the two circuits commonly used in quantum variational algorithms and quantum chemistry on the 5-qubit IBMQ devices by leverage of our optimization algorithm, the experimental results show the optimized circuit has far less error when there exists noise compared to IBM mapping method.
NISQ devices have inherent limitations in terms of connectivity and hardware noise. The synthesis of CNOT circuits considers the physical constraints and transforms quantum algorithms into low-level quantum circuits that can execute on physical chips correctly. In the current trend, quantum chip architectures without Hamiltonian paths are gradually replacing architectures with Hamiltonian paths due to their scalability and low-noise characteristics. To this end, this paper addresses the nearest neighbor synthesis of CNOT circuits in the architectures with and without Hamiltonian paths, aiming to enhance the fidelity of the circuits after execution. Firstly, a key-qubit priority mapping model for general quantum architectures is proposed. Secondly, the initial mapping is further improved by using tabu search to reduce the number of CNOT gates after circuit synthesis and enhance its fidelity. Finally, the noise-aware CNOT circuit nearest neighbor synthesis algorithm for the general architecture is proposed based on the key-qubit priority mapping model. The algorithm is demonstrated on several popular cloud quantum computing platforms and simulators, showing that it effectively optimizes the fidelity of CNOT circuits compared with mainstream methods. Moreover, the method can be extended to more general circuits, thereby improving the overall performance of quantum computing on NISQ devices.