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Optimization of CNOT circuits under topological constraints.

Bujiao Wu, Xiaoyu He, Shuai Yang, Lifu Shou, Guojing Tian, Jialin Zhang, Xiaoming Sun

Published Oct 31, 2019• 5 citations
OpenAlex

Abstract

CNOT circuit is the key gadget for entangling qubits in quantum computing systems. However, the qubit connectivity of noisy intermediate-scale quantum (NISQ) devices is constrained by their topological structures. To improve the performance of CNOT circuits on NISQ devices, we investigate the optimization of the size/depth of CNOT circuits under topological constraints. We firstly present a method that can optimize the size of any $n$-qubit CNOT circuit to less than $2n^2$ on any connected graph, which is optimal for sparsely connected structures. The simulation experiment shows that our method performs better than state-of-the-art results. Specifically, we present two detailed examples to illustrate the applicability of our algorithm. Furthermore, for the future device with a denser structure, we give a better optimization method that achieves $O(n^2/\log \delta)$ size on a graph with the minimum degree $\delta$, which is optimal on the regular graph. Secondly, for the grid structure, which is commonly used in current quantum devices, we demonstrate that the depth of any $n$-qubit CNOT circuit can be optimized to be linear in $n$ with certain ancillary qubits (ancillas). Our experimental results indicate this method has significant improvements compared with all of the existing methods. We further implement the two circuits commonly used in quantum variational algorithms and quantum chemistry on the 5-qubit IBMQ devices by leverage of our optimization algorithm, the experimental results show the optimized circuit has far less error when there exists noise compared to IBM mapping method.

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CNOT circuit is the key gadget for entangling qubits in quantum computing systems. However, the qubit connectivity of noisy intermediate-scale quantum (NISQ) devices is constrained by their topological structures. To improve the performance of CNOT circuits on NISQ devices, we investigate the optimization of the size/depth of CNOT circuits under topological constraints. We firstly present a method that can optimize the size of any nnn-qubit CNOT circuit to less than 2n22n^22n2 on any connected graph, which is optimal for sparsely connected structures. The simulation experiment shows that our method performs better than state-of-the-art results. Specifically, we present two detailed examples to illustrate the applicability of our algorithm. Furthermore, for the future device with a denser structure, we give a better optimization method that achieves O(n2/log⁡δ)O(n^2/\log \delta)O(n2/logδ) size on a graph with the minimum degree δ\deltaδ, which is optimal on the regular graph. Secondly, for the grid structure, which is commonly used in current quantum devices, we demonstrate that the depth of any nnn-qubit CNOT circuit can be optimized to be linear in nnn with certain ancillary qubits (ancillas). Our experimental results indicate this method has significant improvements compared with all of the existing methods. We further implement the two circuits commonly used in quantum variational algorithms and quantum chemistry on the 5-qubit IBMQ devices by leverage of our optimization algorithm, the experimental results show the optimized circuit has far less error when there exists noise compared to IBM mapping method.
A controlled-not (cnot) circuit is the key gadget for entangling qubits in quantum computing systems. However, the qubit connectivity of noisy intermediate-scale quantum (NISQ) devices is constrained by their limited-connectivity architecture. To improve the performance of cnot circuits on NISQ devices, we investigate the optimization of the size/depth of cnot circuits under the limited-connectivity architecture. We present a method that can optimize the size of any nnn-qubit cnot circuit $O(\frac{{n}^{2}}{log\ensuremath{\delta}})$ on any connected graph with minimum degree $\ensuremath{\delta}$, and prove this bound is optimal for the regular graph. For the near-term sparsely connected structure, we additionally present a method that can optimize the size of any nnn-qubit cnot circuit to below 2n22{n}^{2}2n2. The numerical experiment shows that our method performs better than state-of-the-art results. Specifically, we present an example to illustrate the applicability of our algorithm. For the grid structure, which is commonly used in current quantum devices, we demonstrate that the depth of any nnn-qubit cnot circuit can be optimized to be linear in nnn with certain ancillary qubits (ancillas). Experimental results indicate that this method has significant improvements compared with all of the existing methods. We additionally test our algorithms on the five-qubit IBMQ devices, and the experiments show that the measurement results of the optimized circuit with our algorithm are more robust to noise compared with the IBM mapping method.
Abstract Quantum computers in practice today require strict memory constraints, where 2-qubit operations can only be performed between the qubits closest to each other in a graph structure. So a quantum circuit must undergo a transformation to the graph before it can be implemented. In this paper, we study the optimization of the CNOT circuits on some noisy intermediate-scale quantum(NISQ) devices. Compared with previous works, we decompose it into two sub-problems: optimization with a given initial qubit distribution and optimization without limitations of initial qubit distribution. We find that most of the previous researches focused on the first sub-problem, and ignored the influence of different distribution of qubits in the same topology structure on the optimization results. In this paper, we take both sub-problems into account and give some new optimization algorithms. In short, our method is divided into two steps: matrix optimization and routing optimization. We implement matrix optimization with the algorithm in [1 ] and put forward a new heuristic algorithm with MILP method which can solve the second step. We implement our algorithm on IBM20 and some other NISQ devices, the results are better than most other methods in our experiment.
In the near future of the noisy intermediate-scale quantum (NISQ) era, almost all quantum computing devices will be restricted to a specific fixed qubits connectivity architecture. Thus, the synthesis of quantum circuits with limited connectivity is urgent. We design quantum circuit synthesis algorithms for basic and essential synthesis problems, such as quantum state preparation, general unitary synthesis, and quantum isometries. For any architecture, the controlled not (cnot) count is at most 5/3 times the state-of-the-art result on complete-graph architecture. For some specific architectures, such as square-grid ones, the ratio is reduced to 1.126. The numerical simulation result is confirmatory of theoretical conclusions. Our algorithms significantly reduce by more than 5050%50 additional cnot count compared to mapping algorithms. These algorithms help to implement the larger-scale algorithm in the physics device. Our results illustrate that well-designed synthesis algorithms can mitigate the problem of limited qubit connectivity in the NISQ era and may suggest the design of large-scale quantum devices.
Abstract Current quantum computers are noisy intermediate-scale quantum (NISQ) devices. Execution of quantum algorithms, represented as quantum circuits in the quantum circuit model, on such hardware requires transformation of the original circuits to comply with the hardware’s physical constraints, a process known as transpilation. One of the main constraints is limited qubit connectivity. In this work, we present an algorithm that transforms a quantum hashing circuit to satisfy architectural connectivity constraints while minimizing the number of CNOT gates (CNOT cost). The considered algorithm constructs a mapping from logical qubits to physical qubits that minimizes the CNOT cost of the resulting circuit. We optimize circuits for IBM Quantum devices.
Some physical implementation schemes of quantum computing can apply two-qubit gates only on certain pairs of qubits. These connectivity constraints are commonly viewed as a significant disadvantage. For example, compiling an unrestrictednnn-qubit quantum circuit to one with poor qubit connectivity, such as a 1-D chain, usually results in a blowup of depth byO(n2)O(n^{2})O(n2)and size byO(n)O(n)O(n). It is appealing to conjecture that this overhead is unavoidable—a random circuit onnnnqubits hasΘ(n)\Theta (n)Θ(n)two-qubit gates in each layer and a constant fraction of them act on qubits separated by distanceΘ(n)\Theta (n)Θ(n). While it is known that almost allnnn-qubit unitary operations need quantum circuits ofΩ(4n/n)\Omega (4^{n}/n)Ω(4n/n)depth andΩ(4n)\Omega (4^{n})Ω(4n)size to realize with all-to-all qubit connectivity, in this article, we show that allnnn-qubit unitary operations can be implemented by quantum circuits ofO(4n/n)O(4^{n}/n)O(4n/n)depth andO(4n)O(4^{n})O(4n)size even under 1-D chain qubit connectivity constraint. We extend this result and investigate qubit connectivity in three directions. First, we consider more general connectivity graphs and show that the circuit size can always be madeO(4n)O(4^{n})O(4n)as long as the graph is connected. For circuit depth, we studyddd-dimensional grids, completeddd-ary trees and expander graphs, and show results similar to the 1-D chain. Second, we consider the case when ancillary qubits are available. We show that, with ancilla, the circuit depth can be made polynomial, and the space-depth trade-off is not impaired by connectivity constraints unless we have exponentially many ancillary qubits. Third, we obtain nearly optimal results on special families of unitaries, including diagonal unitaries, 2-by-2 block diagonal unitaries, and quantum state preparation (QSP) unitaries, the last being a fundamental task used in many quantum algorithms for machine learning and linear algebra.
In the era of noisy intermediate-scale quantum (NISQ), executing quantum algorithms on actual quantum devices faces unique challenges. One such challenge is that quantum devices in this era have restricted connectivity: quantum gates are allowed to act only on specific pairs of physical qubits. For this reason, a quantum circuit needs to go through a compiling process called qubit routing before it can be executed on a quantum computer. In this study, we propose a CNOT synthesis method called the token reduction method to solve this problem. The token reduction method works for all quantum computers whose architecture is represented by connected graphs. A major difference between our method and the existing ones is that our method synthesizes a circuit to an output qubit mapping that might be different from the input qubit mapping. The final mapping for the synthesis is determined dynamically during the synthesis process. Results showed that our algorithm consistently outperforms the best publicly accessible algorithm for all of the tested quantum architectures.