The surface code is one of the leading quantum error correction codes for realizing large-scale fault-tolerant quantum computing (FTQC). One major challenge in realizing surface-code-based FTQC is the extremely large number of qubits required. To mitigate this problem, fusing multiple codewords of the surface code into a densely packed configuration has been proposed. It is known that by using dense packing, the number of physical qubits required per logical qubit can be reduced to approximately three-fourths compared to simply placing surface-code patches side by side. Despite its potential, concrete deformation procedures and quantitative error-rate analyses have remained largely unexplored. In this work, we present a detailed code-deformation procedure that transforms multiple standard surface code patches into a densely packed, connected configuration, along with a conceptual microarchitecture to utilize this dense packing. We also propose a CNOT gate-scheduling for stabilizer measurement circuits that suppresses hook errors in the densely packed surface code. We performed circuit-level Monte Carlo noise simulation of densely packed surface codes using this gate scheduling. The numerical results demonstrate that as the code distance of the densely packed surface code increases and the physical error rate decreases, the logical error rate of the densely packed surface code becomes lower than that of the standard surface code. Furthermore, we find that only when employing hook-error-avoiding syndrome extraction can the densely packed surface code achieve a lower logical error rate than the standard surface code, while simultaneously reducing the space overhead.
The surface code is one of the leading quantum error correction codes for realizing large-scale fault-tolerant quantum computing (FTQC). One major challenge in realizing surface-code-based FTQC is the extremely large number of qubits required. To mitigate this problem, fusing multiple codewords of the surface code into a densely packed configuration has been proposed. It is known that by using dense packing, the number of physical qubits required per logical qubit can be reduced to approximately three-fourths compared to simply placing surface-code patches side by side. Despite its potential, concrete deformation procedures and quantitative error-rate analyses have remained largely unexplored. In this work, we present a detailed code-deformation procedure that transforms multiple standard surface code patches into a densely packed, connected configuration, along with a conceptual microarchitecture to utilize this dense packing. We also propose a CNOT gate-scheduling for stabilizer measurement circuits that suppresses hook errors in the densely packed surface code. We performed circuit-level Monte Carlo noise simulation of densely packed surface codes using this gate scheduling. The numerical results demonstrate that as the code distance of the densely packed surface code increases and the physical error rate decreases, the logical error rate of the densely packed surface code becomes lower than that of the standard surface code. Furthermore, we find that only when employing hook-error-avoiding syndrome extraction can the densely packed surface code achieve a lower logical error rate than the standard surface code, while simultaneously reducing the space overhead.
Modular quantum computing is a leading candidate for scalable fault tolerant quantum computation. Performing lattice surgery using surface code patches in different modules requires the use of inter-module gates that are noisier than the local gates. Furthermore, the merged layouts during lattice surgery expose multiple directions in which hook errors can propagate to reduce the fault distance. Existing hook-avoiding schedules either increase the syndrome extraction circuit depth, or let link faults propagate into the bulk. We introduce a seam construction that allows splitting arbitrary merged rotated surface code layout into smaller patches with uniform boundaries that could keep their own hook-avoiding N/Z shaped schedule. At the seam we split weight-4 stabilizers into pairs of weight-2 stabilizers that are mediated through a Bell pair and measured within a CNOT depth of 4. We also employ the use of three-qubit CXX gates for parity measurements at the seam to maintain the minimum CNOT depth. Through this seam construction, we confine the elevated link error at the seam, protecting the bulk from higher error rate. We also give a custom detector annotator for such seams that can find the detector space, annotate detectors in the Stim circuits, and ensure that they are suitable to use by matching decoders. We implement our construction for the logical Pauli-XX measurement lattice surgery and a cross-shaped spatial junction and sweep the link error rate from 10 times to 100 times a fixed bulk error rate, and show that our construction gives the lowest and most stable logical error rate than the other frameworks compared here.
We present a quantum code implementable on a regular 2D hex grid with an estimated encoding rate up to 4.5× of that of a rotated surface code patch using circuit-level noise in a one- and two-qubit 10−3 error uniform depolarizing model. Our approach is based on yoking a dense packing of surface code twist defects, enabled by new stabilizer measurement cycles with an optimal four layers of nearest-neighbor two-qubit gates, almost no distance-reducing hook errors, and efficient decoding. We demonstrate a space-efficient architecture for computing on densely packed logical qubits, including new padding-free lattice surgery protocols in an optimal bounding box of 2d2 data and measurement qubits per patch. Assuming a 1μs surface code cycle time and a 10μs reaction time, these developments enable chemically accurate ground state phase estimation of a broad class of `utility-scale' electronic structure simulation problems such as the 108 spin-orbital FeMoco-based nitrogen fixation catalyst in under a month with 89k noisy superconducting qubits. We elucidate a Pareto frontier of space-time trade-offs and find a minimum physical quantum volume of 1.3 mega-qubit-hours. These correspond to a 36× space and 6.6× spacetime improvement, respectively, over our previous state-of-the-art minimum-Toffoli resource estimates (Phys. Rev. X 15, 041016).
In the rotated surface code, hook errors (errors on auxiliary qubits midway through syndrome extraction that propagate to correlated two-qubit data errors) can reduce the circuit-level code distance by a factor of two if the extraction schedule is poorly chosen. The traditional approach uses N-shaped and Z-shaped schedules, selecting the orientation in each plaquette to avoid hook errors aligned with logical operators. However, this becomes increasingly complex within lattice surgery primitives with varied boundary geometries, and requires a 7-step schedule to avoid gate collisions. We propose the diagonal schedule, which orients hook errors along the diagonal of each plaquette. These diagonal errors crucially never align with logical operators regardless of boundary orientation, achieving full code distance. The diagonal schedule is globally uniform: all X-type plaquettes use one schedule and all Z-type plaquettes use another, eliminating geometry-dependent planning. On hardware supporting parallel measurement, reset, and gate operations, the schedule achieves a minimal period of 6 time steps, compared to 7 for the traditional approach. We demonstrate effectiveness for memory experiments, spatial junctions, spatial Hadamard gates, and patch rotation, showing equivalent or improved logical error rates while simplifying circuit construction.
Hook errors are a major challenge in implementing logical operations with the surface code, because they can reduce the fault distance below the code distance. This motivates syndrome-extraction circuits that suppress hook-error effects for the stabilizer layouts that appear during logical operations. However, the existing methods either increase circuit depth or require simultaneous execution of measurements and CNOT gates, both of which introduce additional overheads and degrade the threshold. We propose the ZX interleaving syndrome extraction, which preserves the full fault distance d for any surface-code layout with regular stabilizer tiles at minimum depth, i.e., four layers of CNOT gates, without requiring additional circuit depth or simultaneous execution of measurements and CNOT gates. The key idea is to interleave the Z and X stabilizer tiles so that hook-error edges in the decoding graph are shortened and effectively eliminated. Numerical simulations under uniform depolarizing noise for memory and lattice-surgery experiments confirm that the proposed method achieves a full fault distance of d, whereas the best existing minimum-depth approach achieves d−1. Since the full fault distance is achievable for any regular tiling layout of the surface code, the proposed method may serve as an indispensable technique for practical fault-tolerant quantum computation.
Fault-tolerant quantum computation requires logical operations that manipulate encoded information while preserving quantum error-correction protection. In planar surface-code architectures, code deformation and lattice surgery provide a local, measurement-based route to such operations. Here we experimentally realize key elements of patch-based surface-code logical processing on a 107-qubit superconducting quantum processor. We first implement a reusable primitive layer comprising merge and split, patch expansion and shrinkage, and deformations mediated by domain walls and twist defects. We then compose these primitives to realize logical state routing, the logical controlled-NOT gate, and the single-qubit Hadamard and phase gates, which together form a Clifford-generating set. All operations are implemented on distance-three rotated surface-code patches with multi-round syndrome extraction and neural-network decoding, without post-selection. Our results advance superconducting surface-code experiments from protected logical memory to active, patch-based fault-tolerant logical operations.
Realizing practical quantum computers requires quantum error correction, but the most widely implemented approach, the planar surface code, demands a substantial physical qubit overhead. Here, we demonstrate that partitioning quantum processors into manageable, flat modules with non-local inter-module connections provides a natural solution. By wiring sparse, static boundary connections between Euclidean planar modules, we construct modular hyperbolic surface and color codes, based on new families of semi-hyperbolic codes. Using modular syndrome extraction circuits and efficient neural network and matching decoders, our circuit-level simulations show that this modular memory design can reduce the physical qubit overhead by tenfold or more compared to the surface code, even under elevated inter-module seam error rates. Projecting to larger system sizes, we find modular codes with encoding rate k/n=1/16 and distance d≥22, exceeding both the rate and distance of the [[288,12,18]] two-gross bivariate bicycle code while using mostly nearest-neighbor gates within planar modules, and implying an over 30× overhead reduction relative to surface codes. We develop fault-tolerant walking circuits for implementing logic via code automorphisms, which we co-design with low-weight, highly symmetrical logical bases and a modular extractor system that is ≈4.5× smaller than the code itself. Combining these methods, our modular memory can be used as dense storage in a universal fault-tolerant architecture, unlocking the efficiency of high-rate codes without sacrificing the fabrication advantages of planar modules.