Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Log inSign up
Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Blog
Job Board
Q3AS

© 2026 Aqora Quantum S.A.S.

TermsPrivacyLegal Notice

arXiv:2504.11805 · IEEE International Conference on Quantum Computing and Engineering (QCE)

Network-Integrated Decoding System for Real-Time Quantum Error Correction with Lattice Surgery

Namitha Liyanage, Yue Wu, Emmet Houghton, Lin Zhong

Published Aug 30, 2025• 3 citations
arXivHTMLPDF

Abstract

Existing real-time decoders for surface codes are limited to isolated logical qubits and do not support logical operations involving multiple logical qubits. We present Deconet, a first-of-its-kind decoding system that scales to thousands of logical qubits and supports logical operations implemented through lattice surgery. Deconet organizes compute resources in a network-integrated hybrid tree-grid structure, which results in minimal latency increase and no throughput degradation as the system grows. Specifically, Deconet can be scaled to any arbitrary number of$l$logical qubits by increasing the compute resources by$O(l \times \log (l))$, which provides the required$O(l)$growth in I/O resources while incurring only an$O(\log (l))$increase in latency-a modest growth that is sufficient for thousands of logical qubits. Moreover, we analytically show that the scaling approach preserves throughput, keeping Deconet backlog-free for any number of logical qubits We report an exploratory prototype of Deconet, called Deconet/Helios, built with five VMK-180 FPGAs, that successfully decodes 100 logical qubits of distance five. For 100 logical qubits, under a phenomenological noise rate of$\mathbf{0. 1 \%}$, the Deconet/Helios has an average latency of$2.40 \mu ~\mathrm{s}$and an inverse throughput of 0.84$\mu$s per measurement round.

DOI
10.1109/qce65121.2025.00129

Related papers

Multi-FPGA System for Quantum Error Correction with Lattice Surgery

Namitha Liyanage, Yue Wu, Emmet Houghton +1 more

A practical decoder for quantum error correction must decode a dynamic decoding graph comprising all logical qubits in the system in real-time, a challenging task due to resource limitations. We report HeliosNet, a first-of-its-kind decoding system that overcomes resource constraints through a distributed multi-FPGA architecture. It employs a hybrid treegrid topology to minimize latency for lattice surgery operations distributed across multiple FPGAs. Furthermore, HeliosNet introduces fusion-Union-Find, a novel approach to decoding merged logical qubits that avoids redundant computations associated with traditional window decoders. Additionally, we designed HeliosNet architecture to overcome the IO limitation and minimize data movement latency when integrating with existing quantum control systems. Our exploratory prototype of HeliosNet consists of five Xilinx VMK-180 FPGAs and can decode 100 logical qubits$(d=5)$faster than the rate of measurement. Thus, we believe that HeliosNet is a promising candidate for the logical qubit decoding layer in the quantum computer control stack.

IEEE International Conference on Quantum Computing and Engineering (QCE)•Sep 15, 2024•1 citation

Spatially parallel decoding for multi-qubit lattice surgery

Sophia Fuhui Lin, Eric Peterson, Krishanu Sankar +1 more

Abstract Running quantum algorithms protected by quantum error correction requires a real time, classical decoder. To prevent the accumulation of a backlog, this decoder must process syndromes from the quantum device at a faster rate than they are generated. Most prior work on real time decoding has focused on an isolated logical qubit encoded in the surface code. However, for surface code, quantum programs of utility will require multi-qubit interactions performed via lattice surgery. A large merged patch can arise during lattice surgery—possibly as large as the entire device. This puts a significant strain on a real time decoder, which must decode errors on this merged patch and maintain the level of fault-tolerance that it achieves on isolated logical qubits. These requirements are relaxed by using spatially parallel decoding, which can be accomplished by dividing the physical qubits on the device into multiple overlapping groups and assigning a decoder module to each. We refer to this approach as spatially parallel windows. While previous work has explored similar ideas, none have addressed system-specific considerations pertinent to the task or the constraints from using hardware accelerators. In this work, we demonstrate how to configure spatially parallel windows, so that the scheme (1) is compatible with hardware accelerators, (2) supports general lattice surgery operations, (3) maintains the fidelity of the logical qubits, and (4) meets the throughput requirement for real time decoding. Furthermore, our results reveal the importance of optimally choosing the buffer width to achieve a balance between accuracy and throughput—a decision that should be influenced by the device’s physical noise.

arXiv:2403.01353•Quantum Science and Technology•Mar 28, 2025•6 citations

Real-time Surface-Code Error Correction Using an FPGA-based Neural-Network Decoder

Xiaohan Yang, Xuandong Sun, Zhiyi Wu +9 more

Quantum error correction (QEC) is essential for achieving low error rates required for fault-tolerant quantum computation. In stabilizer-based codes such as the surface code, errors are inferred from repeated syndrome measurements and corrected by a classical decoder. To prevent error accumulation, decoding must be performed with both high throughput and low latency to keep pace with the QEC cycle and enable real-time feedback for universal logical operations. Here we report a hardware-integrated control architecture featuring an FPGA-based neural-network (NN) decoder and experimentally demonstrate real-time surface-code (distance-3) QEC on a superconducting quantum processor. The system achieves a deterministic closed-loop latency of 550 ns, including 124 ns for NN decoding, enabling feedback corrections within a 1.25 us QEC cycle. We show that real-time decoding and feedback correction achieve logical performance comparable to offline decoding while maintaining robustness against varying error conditions. We further demonstrate mid-circuit feedback correction in non-Clifford logical circuits, where Pauli-frame updating alone becomes insufficient. Our results establish a low-latency hardware architecture for embedded QEC control and provide a pathway towards scalable fault-tolerant quantum computing systems.

quant-pharXiv:2605.04892•May 7, 2026•0 citations

Scalable Quantum Error Correction for Surface Codes using FPGA

Namitha Liyanage, Yue Wu, Alexander Deters +1 more

A fault-tolerant quantum computer must decode and correct errors faster than they appear. The faster errors can be corrected, the more time the computer can do useful work. The Union-Find (UF) decoder is promising with an average time complexity slightly higher than $O(d^3)$. We report a distributed version of the UF decoder that exploits parallel computing resources for further speedup. Using an FPGA-based implementation, we empirically show that this distributed UF decoder has a sublinear average time complexity with regard to $d$, given $O(d^3)$ parallel computing resources. The decoding time per measurement round decreases as $d$ increases, a first time for a quantum error decoder. The implementation employs a scalable architecture called Helios that organizes parallel computing resources into a hybrid tree-grid structure. We are able to implement $d$ up to 21 with a Xilinx VCU129 FPGA, for which an average decoding time is 11.5 ns per measurement round under phenomenological noise of 0.1\%, significantly faster than any existing decoder implementation. Since the decoding time per measurement round of Helios decreases with $d$, Helios can decode a surface code of arbitrarily large $d$ without a growing backlog.

arXiv:2301.08419•Jan 20, 2023•1 citation

Real-time decoding of quantum error correction codes using high-performance computing

Lingling Lao, Qiang Wang, Yuanqi Liu +10 more

Quantum error correction (QEC) is indispensable for building scalable fault-tolerant quantum computers. Effective QEC demands stringent real-time decoding: the decoder must process syndrome measurements and determine corrections within a time scale--typically on the order of microseconds, to avoid data backlog. Scaling to large number of logical qubits further necessitates significant computational resources. In this work, we propose an architecture, called \emph{THQLink}, for real-time decoding of quantum error correction codes using high-performance computing (HPC) resources. The network connecting the HPC and the control system of quantum processing unit (QPU) is built on TH-Express and can be adapted to different quantum technologies and their associated control stacks. We report a round-trip latency of 2.944 $μ$s on average, with an incremental overhead of 130 ns per additional hop. Using a parallel window strategy, we demonstrate real-time decoding (1 $μ$s per QEC round) of the surface code up to distance 19 using a matching-based decoder on CPUs. Our work presents a scalable framework for real-time decoding in fault-tolerant quantum computing. It can be readily applied to quantum-centric supercomputers that feature tight integration between QPU and HPC resources, thereby enabling efficient support for hybrid quantum-classical algorithms and computation-intensive workloads offloaded from the QPU.

quant-pharXiv:2608.03948•Aug 5, 2026•0 citations

Scalable Quantum Error Correction for Surface Codes using FPGA

Namitha Liyanage, Yue Wu, Alexander Deters +1 more

A fault-tolerant quantum computer must decode and correct errors faster than they appear. The faster errors can be corrected, the more time the computer can do useful work. The Union-Find (UF) decoder is promising with an average time complexity slightly higher than$O(d^{3})$. We report a distributed version of the UF decoder that exploits parallel computing resources for further speedup. Using an FPGA-based implementation, we empirically show that this distributed UF decoder has a sublinear average time complexity with regard to$d$, given$O(d^{3})$parallel computing resources. The decoding time per measurement round decreases as$d$increases, a first time for a quantum error decoder. The implementation employs a scalable architecture called Helios that organizes parallel computing resources into a hybrid tree-grid structure. Using Xilinx's cycle-accurate simulator, we present cycle-accurate decoding time for$d$up to 15, with the phenomenological noise model with$p=0.1\%$. We are able to implement$d$up to 7 with a Xilinx ZC106 FPGA, for which an average decoding time is 120 ns per measurement round. Since the decoding time per measurement round of Helios decreases with$d$, Helios can decode a surface code of arbitrarily large$d$without a growing backlog.

IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM)•May 1, 2023•14 citations
Existing real-time decoders for surface codes are limited to isolated logical qubits and do not support logical operations involving multiple logical qubits. We present Deconet, a first-of-its-kind decoding system that scales to thousands of logical qubits and supports logical operations implemented through lattice surgery. Deconet organizes compute resources in a network-integrated hybrid tree-grid structure, which results in minimal latency increase and no throughput degradation as the system grows. Specifically, Deconet can be scaled to any arbitrary number ofllllogical qubits by increasing the compute resources byO(l×log⁡(l))O(l \times \log (l))O(l×log(l)), which provides the requiredO(l)O(l)O(l)growth in I/O resources while incurring only anO(log⁡(l))O(\log (l))O(log(l))increase in latency-a modest growth that is sufficient for thousands of logical qubits. Moreover, we analytically show that the scaling approach preserves throughput, keeping Deconet backlog-free for any number of logical qubits We report an exploratory prototype of Deconet, called Deconet/Helios, built with five VMK-180 FPGAs, that successfully decodes 100 logical qubits of distance five. For 100 logical qubits, under a phenomenological noise rate of0.1%\mathbf{0. 1 \%}0.1%, the Deconet/Helios has an average latency of2.40μ s2.40 \mu ~\mathrm{s}2.40μ sand an inverse throughput of 0.84μ\muμs per measurement round.
A practical decoder for quantum error correction must decode a dynamic decoding graph comprising all logical qubits in the system in real-time, a challenging task due to resource limitations. We report HeliosNet, a first-of-its-kind decoding system that overcomes resource constraints through a distributed multi-FPGA architecture. It employs a hybrid treegrid topology to minimize latency for lattice surgery operations distributed across multiple FPGAs. Furthermore, HeliosNet introduces fusion-Union-Find, a novel approach to decoding merged logical qubits that avoids redundant computations associated with traditional window decoders. Additionally, we designed HeliosNet architecture to overcome the IO limitation and minimize data movement latency when integrating with existing quantum control systems. Our exploratory prototype of HeliosNet consists of five Xilinx VMK-180 FPGAs and can decode 100 logical qubits(d=5)(d=5)(d=5)faster than the rate of measurement. Thus, we believe that HeliosNet is a promising candidate for the logical qubit decoding layer in the quantum computer control stack.
Abstract Running quantum algorithms protected by quantum error correction requires a real time, classical decoder. To prevent the accumulation of a backlog, this decoder must process syndromes from the quantum device at a faster rate than they are generated. Most prior work on real time decoding has focused on an isolated logical qubit encoded in the surface code. However, for surface code, quantum programs of utility will require multi-qubit interactions performed via lattice surgery. A large merged patch can arise during lattice surgery—possibly as large as the entire device. This puts a significant strain on a real time decoder, which must decode errors on this merged patch and maintain the level of fault-tolerance that it achieves on isolated logical qubits. These requirements are relaxed by using spatially parallel decoding, which can be accomplished by dividing the physical qubits on the device into multiple overlapping groups and assigning a decoder module to each. We refer to this approach as spatially parallel windows. While previous work has explored similar ideas, none have addressed system-specific considerations pertinent to the task or the constraints from using hardware accelerators. In this work, we demonstrate how to configure spatially parallel windows, so that the scheme (1) is compatible with hardware accelerators, (2) supports general lattice surgery operations, (3) maintains the fidelity of the logical qubits, and (4) meets the throughput requirement for real time decoding. Furthermore, our results reveal the importance of optimally choosing the buffer width to achieve a balance between accuracy and throughput—a decision that should be influenced by the device’s physical noise.
Quantum error correction (QEC) is essential for achieving low error rates required for fault-tolerant quantum computation. In stabilizer-based codes such as the surface code, errors are inferred from repeated syndrome measurements and corrected by a classical decoder. To prevent error accumulation, decoding must be performed with both high throughput and low latency to keep pace with the QEC cycle and enable real-time feedback for universal logical operations. Here we report a hardware-integrated control architecture featuring an FPGA-based neural-network (NN) decoder and experimentally demonstrate real-time surface-code (distance-3) QEC on a superconducting quantum processor. The system achieves a deterministic closed-loop latency of 550 ns, including 124 ns for NN decoding, enabling feedback corrections within a 1.25 us QEC cycle. We show that real-time decoding and feedback correction achieve logical performance comparable to offline decoding while maintaining robustness against varying error conditions. We further demonstrate mid-circuit feedback correction in non-Clifford logical circuits, where Pauli-frame updating alone becomes insufficient. Our results establish a low-latency hardware architecture for embedded QEC control and provide a pathway towards scalable fault-tolerant quantum computing systems.
A fault-tolerant quantum computer must decode and correct errors faster than they appear. The faster errors can be corrected, the more time the computer can do useful work. The Union-Find (UF) decoder is promising with an average time complexity slightly higher than O(d3)O(d^3)O(d3). We report a distributed version of the UF decoder that exploits parallel computing resources for further speedup. Using an FPGA-based implementation, we empirically show that this distributed UF decoder has a sublinear average time complexity with regard to ddd, given O(d3)O(d^3)O(d3) parallel computing resources. The decoding time per measurement round decreases as ddd increases, a first time for a quantum error decoder. The implementation employs a scalable architecture called Helios that organizes parallel computing resources into a hybrid tree-grid structure. We are able to implement ddd up to 21 with a Xilinx VCU129 FPGA, for which an average decoding time is 11.5 ns per measurement round under phenomenological noise of 0.1\%, significantly faster than any existing decoder implementation. Since the decoding time per measurement round of Helios decreases with ddd, Helios can decode a surface code of arbitrarily large ddd without a growing backlog.
Quantum error correction (QEC) is indispensable for building scalable fault-tolerant quantum computers. Effective QEC demands stringent real-time decoding: the decoder must process syndrome measurements and determine corrections within a time scale--typically on the order of microseconds, to avoid data backlog. Scaling to large number of logical qubits further necessitates significant computational resources. In this work, we propose an architecture, called \emph{THQLink}, for real-time decoding of quantum error correction codes using high-performance computing (HPC) resources. The network connecting the HPC and the control system of quantum processing unit (QPU) is built on TH-Express and can be adapted to different quantum technologies and their associated control stacks. We report a round-trip latency of 2.944 μμμs on average, with an incremental overhead of 130 ns per additional hop. Using a parallel window strategy, we demonstrate real-time decoding (1 μμμs per QEC round) of the surface code up to distance 19 using a matching-based decoder on CPUs. Our work presents a scalable framework for real-time decoding in fault-tolerant quantum computing. It can be readily applied to quantum-centric supercomputers that feature tight integration between QPU and HPC resources, thereby enabling efficient support for hybrid quantum-classical algorithms and computation-intensive workloads offloaded from the QPU.
A fault-tolerant quantum computer must decode and correct errors faster than they appear. The faster errors can be corrected, the more time the computer can do useful work. The Union-Find (UF) decoder is promising with an average time complexity slightly higher thanO(d3)O(d^{3})O(d3). We report a distributed version of the UF decoder that exploits parallel computing resources for further speedup. Using an FPGA-based implementation, we empirically show that this distributed UF decoder has a sublinear average time complexity with regard toddd, givenO(d3)O(d^{3})O(d3)parallel computing resources. The decoding time per measurement round decreases asdddincreases, a first time for a quantum error decoder. The implementation employs a scalable architecture called Helios that organizes parallel computing resources into a hybrid tree-grid structure. Using Xilinx's cycle-accurate simulator, we present cycle-accurate decoding time fordddup to 15, with the phenomenological noise model withp=0.1%p=0.1\%p=0.1%. We are able to implementdddup to 7 with a Xilinx ZC106 FPGA, for which an average decoding time is 120 ns per measurement round. Since the decoding time per measurement round of Helios decreases withddd, Helios can decode a surface code of arbitrarily largedddwithout a growing backlog.