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IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM)

Scalable Quantum Error Correction for Surface Codes using FPGA

Namitha Liyanage, Yue Wu, Alexander Deters, Lin Zhong

Published May 1, 2023• 14 citations
Publisher

Abstract

A fault-tolerant quantum computer must decode and correct errors faster than they appear. The faster errors can be corrected, the more time the computer can do useful work. The Union-Find (UF) decoder is promising with an average time complexity slightly higher than$O(d^{3})$. We report a distributed version of the UF decoder that exploits parallel computing resources for further speedup. Using an FPGA-based implementation, we empirically show that this distributed UF decoder has a sublinear average time complexity with regard to$d$, given$O(d^{3})$parallel computing resources. The decoding time per measurement round decreases as$d$increases, a first time for a quantum error decoder. The implementation employs a scalable architecture called Helios that organizes parallel computing resources into a hybrid tree-grid structure. Using Xilinx's cycle-accurate simulator, we present cycle-accurate decoding time for$d$up to 15, with the phenomenological noise model with$p=0.1\%$. We are able to implement$d$up to 7 with a Xilinx ZC106 FPGA, for which an average decoding time is 120 ns per measurement round. Since the decoding time per measurement round of Helios decreases with$d$, Helios can decode a surface code of arbitrarily large$d$without a growing backlog.

DOI
10.1109/fccm57271.2023.00045

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A fault-tolerant quantum computer must decode and correct errors faster than they appear. The faster errors can be corrected, the more time the computer can do useful work. The Union-Find (UF) decoder is promising with an average time complexity slightly higher thanO(d3)O(d^{3})O(d3). We report a distributed version of the UF decoder that exploits parallel computing resources for further speedup. Using an FPGA-based implementation, we empirically show that this distributed UF decoder has a sublinear average time complexity with regard toddd, givenO(d3)O(d^{3})O(d3)parallel computing resources. The decoding time per measurement round decreases asdddincreases, a first time for a quantum error decoder. The implementation employs a scalable architecture called Helios that organizes parallel computing resources into a hybrid tree-grid structure. Using Xilinx's cycle-accurate simulator, we present cycle-accurate decoding time fordddup to 15, with the phenomenological noise model withp=0.1%p=0.1\%p=0.1%. We are able to implementdddup to 7 with a Xilinx ZC106 FPGA, for which an average decoding time is 120 ns per measurement round. Since the decoding time per measurement round of Helios decreases withddd, Helios can decode a surface code of arbitrarily largedddwithout a growing backlog.
A fault-tolerant quantum computer must decode and correct errors faster than they appear. The faster errors can be corrected, the more time the computer can do useful work. The Union-Find (UF) decoder is promising with an average time complexity slightly higher thanO(d3O(d^{3}O(d3. We report a distributed version of the UF decoder that exploits parallel computing resources for further speedup. Using an FPGA-based implementation, we empirically show that this distributed UF decoder hasaaasublinear average time complexity with regard todddgivenO(d3O(d^{3}O(d3parallel computing resources. The decoding time per measurement round decreases asdddincreases, a first time for a quantum error decoder. The implementation employs a scalable architecture called Helios that organizes parallel computing resources into a hybrid tree-grid structure. We are able to implementdddup to 21 with a Xilinx VCU129 FPGA, for which an average decoding time is 11.5 ns per measurement round under phenomenological noise of 0.1 %, significantly faster than any existing decoder implementation. Since the decoding time per measurement round of Helios decreases with d, Helios can decode a surface code of arbitrarily largedddwithout a growing backlog.
A fault-tolerant quantum computer must decode and correct errors faster than they appear. The faster errors can be corrected, the more time the computer can do useful work. The Union-Find (UF) decoder is promising with an average time complexity slightly higher than O(d3)O(d^3)O(d3). We report a distributed version of the UF decoder that exploits parallel computing resources for further speedup. Using an FPGA-based implementation, we empirically show that this distributed UF decoder has a sublinear average time complexity with regard to ddd, given O(d3)O(d^3)O(d3) parallel computing resources. The decoding time per measurement round decreases as ddd increases, a first time for a quantum error decoder. The implementation employs a scalable architecture called Helios that organizes parallel computing resources into a hybrid tree-grid structure. We are able to implement ddd up to 21 with a Xilinx VCU129 FPGA, for which an average decoding time is 11.5 ns per measurement round under phenomenological noise of 0.1\%, significantly faster than any existing decoder implementation. Since the decoding time per measurement round of Helios decreases with ddd, Helios can decode a surface code of arbitrarily large ddd without a growing backlog.
Fast decoders that achieve strong error suppression are essential for fault-tolerant quantum computation (FTQC) from both practical and theoretical perspectives. The union-find (UF) decoder for the surface code is widely regarded as a promising candidate, offering almost-linear time complexity and favorable empirical error suppression supported by numerical evidence. However, the lack of a rigorous threshold theorem has left open whether the UF decoder can achieve fault tolerance beyond the error models and parameter regimes tested in numerical simulations. Here, we provide a rigorous proof of a finite threshold for the UF decoder on the surface code under the circuit-level local stochastic error model. To this end, we develop a refined error-clustering framework that extends techniques previously used to analyze cellular-automaton and renormalization-group decoders, by showing that error clusters can be separated by substantially larger buffers, thereby enabling analytical control over the behavior of the UF decoder. Using this guarantee, we further prove a quasi-polylogarithmic upper bound on the average runtime of a parallel UF decoder in terms of the code size. We also show that this framework yields a finite threshold for the greedy decoder, a simpler decoder with lower complexity but weaker empirical error suppression. These results provide a solid theoretical foundation for the practical use of UF-based decoders in the development of fault-tolerant quantum computers, while offering a unified framework for studying fault tolerance across these practical decoders.
A fault-tolerant quantum computer must decode and correct errors faster than they appear to prevent exponential slowdown due to error correction. The Union-Find (UF) decoder is promising with an average time complexity slightly higher thanO(d3)O(d^{3})O(d3). We report a distributed version of the UF decoder that exploits parallel computing resources for further speedup. Using a field-programmable gate array (FPGA)-based implementation, we empirically show that this distributed UF decoder has a sublinear average time complexity with regard toddd, givenO(d3)O(d^{3})O(d3)parallel computing resources. The decoding time per measurement round decreases asdddincreases, the first time for a quantum error decoder. The implementation employs a scalable architecture called Helios that organizes parallel computing resources into a hybrid tree-grid structure. Using a Xilinx VCU129 FPGA, we successfully implementdddup to 21 with an average decoding time of 11.5 ns per measurement round under 0.1% phenomenological noise and 23.7 ns ford=17d=17d=17under equivalent circuit-level noise. This performance is significantly faster than any existing decoder implementation. Furthermore, we show that Helios can optimize for resource efficiency by decodingd=51d=51d=51on a Xilinx VCU129 FPGA with an average latency of 544 ns per measurement round.
Quantum error correction (QEC) is indispensable for building scalable fault-tolerant quantum computers. Effective QEC demands stringent real-time decoding: the decoder must process syndrome measurements and determine corrections within a time scale--typically on the order of microseconds, to avoid data backlog. Scaling to large number of logical qubits further necessitates significant computational resources. In this work, we propose an architecture, called \emph{THQLink}, for real-time decoding of quantum error correction codes using high-performance computing (HPC) resources. The network connecting the HPC and the control system of quantum processing unit (QPU) is built on TH-Express and can be adapted to different quantum technologies and their associated control stacks. We report a round-trip latency of 2.944 μμμs on average, with an incremental overhead of 130 ns per additional hop. Using a parallel window strategy, we demonstrate real-time decoding (1 μμμs per QEC round) of the surface code up to distance 19 using a matching-based decoder on CPUs. Our work presents a scalable framework for real-time decoding in fault-tolerant quantum computing. It can be readily applied to quantum-centric supercomputers that feature tight integration between QPU and HPC resources, thereby enabling efficient support for hybrid quantum-classical algorithms and computation-intensive workloads offloaded from the QPU.
Real-time Quantum Error Correction (QEC) for Fault-Tolerant Quantum Computing (FTQC) demands immediate surface code decoding with both high accuracy and low latency. The highly accurate Union-Find (UF) algorithm has traditionally been limited to batch-processing, as its iterative cluster growth is incompatible with the concurrent initiation of decoding with each syndrome measurement round, required for real-time QEC. This research presents a novel online UF decoder microarchitecture designed to overcome these limitations. Our key innovation decomposes UF cluster growth into incremental, per-cycle steps managed by a dedicated SHIFT stage. ASIC evaluation of our implementation demonstrates a102.38\mathbf{1 0 2. 3 8}102.38ns latency for a surface code with a distance of 23 and an approximate 1.4% threshold, meeting critical QEC performance targets. By demonstrating a viable online UF decoder with competitive performance, this research offers a crucial building block for the practical realization of scalable FTQC.