. We report a distributed version of the UF decoder that exploits parallel computing resources for further speedup. Using an FPGA-based implementation, we empirically show that this distributed UF decoder has a sublinear average time complexity with regard to

d

, given

O(d^3)

parallel computing resources. The decoding time per measurement round decreases as

d

increases, a first time for a quantum error decoder. The implementation employs a scalable architecture called Helios that organizes parallel computing resources into a hybrid tree-grid structure. We are able to implement

d

up to 21 with a Xilinx VCU129 FPGA, for which an average decoding time is 11.5 ns per measurement round under phenomenological noise of 0.1%, significantly faster than any existing decoder implementation. Since the decoding time per measurement round of Helios decreases with

d

, Helios can decode a surface code of arbitrarily large

d

without a growing backlog.

DOI: 10.48550/arxiv.2301.08419

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O(d^3)

d

, given

O(d^3)

parallel computing resources. The decoding time per measurement round decreases as

d

d

d

, Helios can decode a surface code of arbitrarily large

d

without a growing backlog.

O(d^{3}

a

sublinear average time complexity with regard to

d

given

O(d^{3}

parallel computing resources. The decoding time per measurement round decreases as

d

d

up to 21 with a Xilinx VCU129 FPGA, for which an average decoding time is 11.5 ns per measurement round under phenomenological noise of 0.1 %, significantly faster than any existing decoder implementation. Since the decoding time per measurement round of Helios decreases with d, Helios can decode a surface code of arbitrarily large

d

without a growing backlog.

O(d^{3})

d

, given

O(d^{3})

parallel computing resources. The decoding time per measurement round decreases as

d

d

up to 15, with the phenomenological noise model with

p=0.1\%

. We are able to implement

d

up to 7 with a Xilinx ZC106 FPGA, for which an average decoding time is 120 ns per measurement round. Since the decoding time per measurement round of Helios decreases with

d

, Helios can decode a surface code of arbitrarily large

d

without a growing backlog.

O(d^{3})

. We report a distributed version of the UF decoder that exploits parallel computing resources for further speedup. Using a field-programmable gate array (FPGA)-based implementation, we empirically show that this distributed UF decoder has a sublinear average time complexity with regard to

d

, given

O(d^{3})

parallel computing resources. The decoding time per measurement round decreases as

d

increases, the first time for a quantum error decoder. The implementation employs a scalable architecture called Helios that organizes parallel computing resources into a hybrid tree-grid structure. Using a Xilinx VCU129 FPGA, we successfully implement

d

up to 21 with an average decoding time of 11.5 ns per measurement round under 0.1% phenomenological noise and 23.7 ns for

d=17

under equivalent circuit-level noise. This performance is significantly faster than any existing decoder implementation. Furthermore, we show that Helios can optimize for resource efficiency by decoding

d=51

on a Xilinx VCU129 FPGA with an average latency of 544 ns per measurement round.

μ

s on average, with an incremental overhead of 130 ns per additional hop. Using a parallel window strategy, we demonstrate real-time decoding (1

μ

s per QEC round) of the surface code up to distance 19 using a matching-based decoder on CPUs. Our work presents a scalable framework for real-time decoding in fault-tolerant quantum computing. It can be readily applied to quantum-centric supercomputers that feature tight integration between QPU and HPC resources, thereby enabling efficient support for hybrid quantum-classical algorithms and computation-intensive workloads offloaded from the QPU.

\mathbf{1 0 2. 3 8}

ns latency for a surface code with a distance of 23 and an approximate 1.4% threshold, meeting critical QEC performance targets. By demonstrating a viable online UF decoder with competitive performance, this research offers a crucial building block for the practical realization of scalable FTQC.