Quantum Error Correction (QEC) codes form the foundation of Fault-Tolerant Quantum Computing (FTQC) and predominantly use the Clifford+T gate set. Recently, Clifford operations have become the key performance bottleneck in implementing QEC. While state-of-the-art approaches like Pauli-Based Compilation (PBC) reduce Clifford overhead by transforming Clifford gates into Pauli measurements, they do so at the cost of gate-level parallelism, inflating circuit depth and execution times. To overcome these limitations, we introduce TACO, a Transpiler-Architecture Co-design framework that tackles the Clifford bottleneck through circuit and architectural optimization. TACO uses FTQC insights to guide hardware-aware Clifford gate elimination and circuit restructuring, and leverages the resulting optimized circuits to refine architectural design. TACO applies FTQC-specific transformations to aggressively reduce Clifford overhead from rotation synthesis and Toffoli decompositions, while preserving gate-level parallelism. The resulting architecture is optimized for the locality and data-movement patterns of these circuits, enabling high-throughput, resource-efficient execution. Our evaluation across diverse benchmarks shows that TACO achieves up to 21.9x (mean 4.4x) reduction in execution time compared to the state-of-the-art baseline.
Quantum Error Correction (QEC) codes form the foundation of Fault-Tolerant Quantum Computing (FTQC) and predominantly use the Clifford+T gate set. Recently, Clifford operations have become the key performance bottleneck in implementing QEC. While state-of-the-art approaches like Pauli-Based Compilation (PBC) reduce Clifford overhead by transforming Clifford gates into Pauli measurements, they do so at the cost of gate-level parallelism, inflating circuit depth and execution times. To overcome these limitations, we introduce TACO, a Transpiler-Architecture Co-design framework that tackles the Clifford bottleneck through circuit and architectural optimization. TACO uses FTQC insights to guide hardware-aware Clifford gate elimination and circuit restructuring, and leverages the resulting optimized circuits to refine architectural design. TACO applies FTQC-specific transformations to aggressively reduce Clifford overhead from rotation synthesis and Toffoli decompositions, while preserving gate-level parallelism. The resulting architecture is optimized for the locality and data-movement patterns of these circuits, enabling high-throughput, resource-efficient execution. Our evaluation across diverse benchmarks shows that TACO achieves up to 21.9x (mean 4.4x) reduction in execution time compared to the state-of-the-art baseline.
Scalable quantum computation is expected to rely on fault-tolerant quantum computation (FTQC), in which quantum error correction (QEC) suppresses physical errors sufficiently to support reliable logical operations. This requires quantum compilation to move beyond general-purpose circuit optimization toward encoding-aware and protocol-structured compilation across the full stack of fault-tolerant quantum computers. Beyond circuit synthesis and hardware mapping, an FTQC compiler must lower algorithm-level operations into the logical gate set supported by the chosen code, coordinate encoded data and ancilla resources, realize logical operations together with repeated syndrome extraction under hardware constraints, and provide the resulting measurement stream to real-time decoding.
This survey presents a full-stack view of compiler design for QEC-protected quantum computation. We organize existing work into three interacting layers: logical-level QEC compilation, physical-level QEC realization, and decoder runtime integration. At the logical level, we review surface-code lattice-surgery compilers, beyond-surface-code code-surgery frameworks including emerging qLDPC approaches, and compilation support for non-Clifford operations such as magic-state distillation and code switching. At the physical level, we survey hardware-aware QEC realization on superconducting, trapped-ion, and neutral-atom platforms. We further examine decoder models, real-time decoding systems, and frame-management mechanisms that close the feedback loop during fault-tolerant execution. Finally, we identify open challenges in cross-layer optimization, qLDPC compilation, compiler-decoder co-design, runtime adaptivity, and the development of integrated and benchmarkable FTQC compilation stacks. An actively maintained paper list is available at: github.com/chenghongz/QEC-compiler-design.
Surface codes represent a leading approach for quantum error correction (QEC), offering a path towards universal fault-tolerant quantum computing (FTQC). However, efficiently implementing algorithms, particularly using Pauli-based computation (PBC) with lattice surgery, necessitates careful resource optimization. Prior work often employs static layouts and simplified error models. These typically fail to capture the full costs and dynamic nature of active computation, leading to resource bottlenecks and suboptimal architectural designs. To address this, we introduce SPARO. SPARO features a comprehensive logical error model based on a large corpus of numerical simulations encompassing active Pauli-based computation (PBC) operations-including Pauli product measurements (PPMs), idling qubits, and patch rotations. Our numerical models are integrated within an end-to-end compilation pipeline. SPARO analyzes algorithm-specific bottlenecks arising from constraints such as limited routing areas or magic-state factory throughput. SPARO then dynamically allocates available hardware resources, balancing compute, routing, and magic-state distillation, to minimize space-time overhead and logical error rates for specific workloads. Our simulations demonstrate that SPARO effectively identifies critical resource trade-offs. When evaluated on benchmark circuits, SPARO identifies resource configurations achieving up to 51.11% logical error rate reductions for 433-qubit ADDER circuits when compared to state-of-the-art static layouts using an identical total resource budget. This dynamic approach enables effective co-optimization of PBC execution and surface-code architectures, significantly improving overall resource efficiency. SPARO will be open sourced.
Quantum computing is positioned to be a transformative technology to key areas of scientific interest such as quantum chemistry, material science, and cryptography. At a hardware level, recent years have seen broad progress in a variety of qubit modalities, however, error rates are still orders of magnitude higher than what is necessary for large-scale quantum programs. This gap in error rates motivates the use of quantum error correction (QEC) and the realization of fault-tolerant quantum computing (FTQC), yet today, although the theory of FTQC is promising, effectively connecting it to real devices poses significant challenges. In this dissertation we study opportunities for more efficient and scalable FTQC architectures through the co-design of quantum hardware and software. We first look at how unique hardware capabilities in quantum computers made from 2D arrays of optically trapped atoms can improve QEC performance. For computation, we study how longer-range interactions between atoms can enable a novel embedding of QEC blocks on physical qubits that improves logical-level connectivity. For memory, we study how mid-circuit movement of atoms can effectively implement higher encoding rate QEC codes, creating a qubit-efficient memory system. We next consider the performance impact of real-time classical systems in FTQC architectures, and explore the use of speculation to improve large-scale decoding systems. Finally, we study how software systems can be used to improve QEC designs. We consider the problem of QEC circuit optimization, and study an automated approach based on iterative optimization of performance-reducing subcircuits.
Neutral-atom arrays are a leading qubit technology for large-scale, fault-tolerant quantum computing (FTQC). A dominant error source on this platform is qubit loss, which accrues with every operation and movement. The presence of loss undermines the promises of existing architectural work. Standard error correction targets stochastic Pauli errors and cannot correct loss, so most FTQC performance analyses are not directly compatible with it. Moreover, compilation and routing decisions, which strongly affect overall loss, are typically optimized against Pauli-error cost models and often remain loss-agnostic, potentially increasing exposure to the loss channel.
In this work, we comprehensively model the effect of qubit loss on neutral-atom FTQC and develop a loss-tolerant transversal-gate architecture. We treat loss not as a predetermined error parameter but as a dynamic budget spent across a whole program, allowing us to control it by co-designing layout, compilation, and decoding. We target a physical implementation with no separate storage and entangling zones, eliminating the repeated SLM-AOD handoffs and long-distance shuttling that dominate loss in other layouts. We develop compiler optimizations that maximize gate parallelism while respecting the RF tone budget and AOD bandwidth constraints. Our work couples these with a loss-aware, delayed-erasure decoder and an end-to-end loss-aware magic state cultivation protocol. Overall, we improve accumulated loss per syndrome-extraction round by up to 2.15X against a zoned baseline and reduce logical error rates by over two orders of magnitude versus current architectures. Our framework also informs concrete device targets such as continuous reloading rates, AOD counts, and shuttling trajectory choices. We expect these insights to matter for system architects as neutral-atom hardware scales.
Early modular fault tolerant quantum computers remain constrained by costly inter-module communication and limited magic state factory service. Understanding such bottlenecks and investigating compiler optimizations most close the gap between algorithm requirements and hardware capabilities is a concrete and practically urgent systems problem. We study the modular architectures based on Bivariate Bicycle codes and identify the dominant bottleneck: inter-module communication induced by non-Clifford operations. We build a compilation pipeline to fill the missing parts of prior works and propose compiler optimizations: synthesizing arbitrary-angle rotations at the factory (syn@fac), transvection based Clifford deferral, and Clifford insertion for critical path duration reduction. We extend the evaluation scope of the prior work to 40+ benchmark categories drawn from PennyLane and MQTBench, including quantum algorithms and Hamiltonian simulations with varying sizes. Under the present instruction cost, syn@fac reduces estimated circuit failure probability by a factor of 9.0 on average across non-Clifford benchmarks. The robustness persists across sweeps of instruction cost ratios, LPU count, and factory count. Besides, transvection reduces Clifford deferral compile time by 77.04\%, while Clifford insertion reduces end-to-end circuit duration by 11.54\% on average on MQTBench, with smaller gains on Hamiltonian simulations. We hope this work inspires the studies on compiler optimizations for early modular FTQC systems.
Quantum computing has the potential to transform modern computation by offering exponential advantages in areas such as cryptography, optimization, and intelligent data processing. To effectively realize these advantages, particularly in fault-tolerant and Noisy Intermediate-Scale Quantum (NISQ) environments, quantum circuits must be both resource-efficient and error-resilient. This paper presents a novel Binary-Coded Decimal (BCD) to Excess-3 code converter designed exclusively using the Clifford+T gate set, which is widely supported by fault-tolerant quantum hardware. The proposed design eliminates conventional 4-bit reversible adder-based implementations and instead employs an optimized logic structure based on Clifford+T-decomposed Peres gates. By leveraging Temporary Logical-AND gates and CNOT operations, the circuit achieves reduced T-count, circuit depth, and quantum cost as key metrics in fault-tolerant quantum computation. Functional correctness is verified through IBM Qiskit, Version 2.1 simulations for all valid BCD inputs. The proposed converter serves as a scalable and hardware-compatible arithmetic building block for resource-aware and AI-oriented quantum architectures.