Surface codes represent a leading approach for quantum error correction (QEC), offering a path towards universal fault-tolerant quantum computing (FTQC). However, efficiently implementing algorithms, particularly using Pauli-based computation (PBC) with lattice surgery, necessitates careful resource optimization. Prior work often employs static layouts and simplified error models. These typically fail to capture the full costs and dynamic nature of active computation, leading to resource bottlenecks and suboptimal architectural designs. To address this, we introduce SPARO. SPARO features a comprehensive logical error model based on a large corpus of numerical simulations encompassing active Pauli-based computation (PBC) operations-including Pauli product measurements (PPMs), idling qubits, and patch rotations. Our numerical models are integrated within an end-to-end compilation pipeline. SPARO analyzes algorithm-specific bottlenecks arising from constraints such as limited routing areas or magic-state factory throughput. SPARO then dynamically allocates available hardware resources, balancing compute, routing, and magic-state distillation, to minimize space-time overhead and logical error rates for specific workloads. Our simulations demonstrate that SPARO effectively identifies critical resource trade-offs. When evaluated on benchmark circuits, SPARO identifies resource configurations achieving up to 51.11% logical error rate reductions for 433-qubit ADDER circuits when compared to state-of-the-art static layouts using an identical total resource budget. This dynamic approach enables effective co-optimization of PBC execution and surface-code architectures, significantly improving overall resource efficiency. SPARO will be open sourced.
Surface codes represent a leading approach for quantum error correction (QEC), offering a path towards universal fault-tolerant quantum computing (FTQC). However, efficiently implementing algorithms, particularly using Pauli-based computation (PBC) with lattice surgery, necessitates careful resource optimization. Prior work often employs static layouts and simplified error models. These typically fail to capture the full costs and dynamic nature of active computation, leading to resource bottlenecks and suboptimal architectural designs. To address this, we introduce SPARO. SPARO features a comprehensive logical error model based on a large corpus of numerical simulations encompassing active Pauli-based computation (PBC) operations-including Pauli product measurements (PPMs), idling qubits, and patch rotations. Our numerical models are integrated within an end-to-end compilation pipeline. SPARO analyzes algorithm-specific bottlenecks arising from constraints such as limited routing areas or magic-state factory throughput. SPARO then dynamically allocates available hardware resources, balancing compute, routing, and magic-state distillation, to minimize space-time overhead and logical error rates for specific workloads. Our simulations demonstrate that SPARO effectively identifies critical resource trade-offs. When evaluated on benchmark circuits, SPARO identifies resource configurations achieving up to 51.11% logical error rate reductions for 433-qubit ADDER circuits when compared to state-of-the-art static layouts using an identical total resource budget. This dynamic approach enables effective co-optimization of PBC execution and surface-code architectures, significantly improving overall resource efficiency. SPARO will be open sourced.
Toward the large-scale, practical realization of quantum computing, quantum error correction is essential. Among various quantum error-correcting codes, the surface code stands out as a leading candidate, and lattice surgery based on surface codes has emerged as a promising technique for fault-tolerant quantum computation (FTQC). However, implementing quantum algorithms using lattice surgery introduces both resource and time overhead. Existing approaches typically focus on large layout designs, with compiler passes aimed primarily at optimizing time overhead. This often overlooks the trade-off between rotation bottlenecks and movement distance, which leads to inefficient resource utilization and prevents further reduction of the quantum computation failure rate.
To address these challenges, we introduce O3LS, a framework for optimizing lattice surgery through automatic layout search and loose scheduling. O3LS achieves an optimal balance by automatically generating squeezed data layouts to reduce space requirements and employing loose scheduling algorithms combined with circuit synthesis techniques to reduce time overhead, thereby effectively minimizing overall logical error rates. Numerical results indicate that O3LS can reduce space overhead by 28.0% over standard layouts and 46.7% over sparse layouts without increasing the number of time steps, leading to suppression of logical error rates by up to 16% relative to larger data layout designs. O3LS can also achieve time overhead reductions of 36.07% and 24.76% in compact and standard data layout designs, respectively. It suppresses logical error rates by up to an order of magnitude compared to prior compilers that focus primarily on maximizing parallelism.
Quantum Error Correction (QEC) is essential for future quantum computers due to its ability to exponentially suppress physical errors. The surface code is a leading error-correcting code candidate because of its local topological structure, experimentally achievable thresholds, and support for universal gate operations with magic states. However, its physical overhead scales quadratically with number of correctable errors. Conversely, quantum low-density parity-check (qLDPC) codes offer superior scaling but lack, on their own, a clear path to universal logical computation. Therefore, it is becoming increasingly evident is becoming that there are significant advantages to designing architectures using multiple codes. Heterogeneous architectures provide a clear path to universal logical computation as well as the ability to access different resource trade offs. To address this, we propose integrating the surface code and gross code using an ancilla bus for inter-code data movement. This approach involves managing trade-offs, including qubit overhead, a constrained instruction set, and gross code (memory) routing and management. While our focus is on the gross-surface code architecture, our method is adaptable to any code combination and the constraints generated by that specific architecture. Motivated by the potential reduction of physical qubit overhead, an ever important feature in the realization of fault tolerant computation, we perform the first full system study of heterogeneous error-correcting codes, discovering architectural trade-offs and optimizing around them. We demonstrate physical qubit reductions of up to 6.42x when executing an algorithm to a specific logical error rate, at the cost of up to a 3.43x increase in execution time.
Scalable quantum computation is expected to rely on fault-tolerant quantum computation (FTQC), in which quantum error correction (QEC) suppresses physical errors sufficiently to support reliable logical operations. This requires quantum compilation to move beyond general-purpose circuit optimization toward encoding-aware and protocol-structured compilation across the full stack of fault-tolerant quantum computers. Beyond circuit synthesis and hardware mapping, an FTQC compiler must lower algorithm-level operations into the logical gate set supported by the chosen code, coordinate encoded data and ancilla resources, realize logical operations together with repeated syndrome extraction under hardware constraints, and provide the resulting measurement stream to real-time decoding.
This survey presents a full-stack view of compiler design for QEC-protected quantum computation. We organize existing work into three interacting layers: logical-level QEC compilation, physical-level QEC realization, and decoder runtime integration. At the logical level, we review surface-code lattice-surgery compilers, beyond-surface-code code-surgery frameworks including emerging qLDPC approaches, and compilation support for non-Clifford operations such as magic-state distillation and code switching. At the physical level, we survey hardware-aware QEC realization on superconducting, trapped-ion, and neutral-atom platforms. We further examine decoder models, real-time decoding systems, and frame-management mechanisms that close the feedback loop during fault-tolerant execution. Finally, we identify open challenges in cross-layer optimization, qLDPC compilation, compiler-decoder co-design, runtime adaptivity, and the development of integrated and benchmarkable FTQC compilation stacks. An actively maintained paper list is available at: github.com/chenghongz/QEC-compiler-design.
Pauli-based computation (PBC) provides a universal framework for executing fault-tolerant quantum algorithms using Pauli measurements and magic states. In monolithic architectures, the serialized nature of PBC directly ties runtime to a circuit's T-gate count, making it slow on metrics like circuit depth. However, in distributed quantum computing (DQC), the primary bottleneck is remote Bell pair generation. We investigate the tradeoff between error-correcting code block size and execution time of PBC within the Q-Fly architecture at intermediate scale, limiting individual node capacities to reflect near-term constraints while supplying abundant network nodes to minimize routing and compilation effects. We find that large qLDPC code blocks outperform the surface code baseline in terms of execution time by up to an order of magnitude when evaluated against quantum optimization algorithms. By moving groups of qubits to free nodes to bypass the sequential bottleneck of PBC, the large-block architecture minimizes network operations and achieves faster overall execution. This demonstrates that PBC is a competitive model in the distributed regime, establishing it as a practical compilation baseline for qLDPC systems before invoking more efficient transversal or homological gates.
Fault-tolerant quantum computing (FTQC) is required to execute quantum algorithms capable of tackling computationally intractable problems in chemistry, material science, and cryptography. Noisy Intermediate-Scale Quantum (NISQ) devices remain constrained by physical error rates that degrade quantum coherence over short circuit depths. Quantum error correction (QEC) protects fragile logical states by encoding them into non-local degrees of freedom across topological physical qubit arrays. This research presents a comprehensive architectural and theoretical evaluation of three primary QEC paradigms: planar surface codes, topological color codes, and asymptotic quantum low-density parity-check (qLDPC) codes. We examine error thresholds, transversal gate constraints governed by the Eastin-Knill theorem, magic state distillation (MSD) overheads, lattice surgery, and classical decoding latencies across superconducting transmons, trapped ions, and neutral atom platforms.
Fault-tolerant quantum computing (FTQC) is emerging as the architectural regime in which practical large-scale quantum workloads will execute. In this setting, however, multiprogramming is no longer a matter of partitioning a flat pool of qubits. Quantum error correction exposes a structured floorplan of data tiles, ancilla tiles, and magic-state service resources, so concurrent execution must account for compact placement, connectivity, routing headroom, and shared support infrastructure. This makes FTQC multiprogramming fundamentally harder than its NISQ counterpart: admission decisions can fragment the remaining floorplan, conservative reservations can waste ancilla, and dynamic contention across data, ancilla, and magic-state resources can degrade both throughput and quality of service. In this work, we develop a formal framework for FTQC multiprogramming that captures these structural constraints and their runtime implications. We formulate the baseline static allocation problem, extend it to limited-resource and online settings through hierarchy-aware scheduling policies, and further generalize it to cultivation-enabled architectures with dynamic magic-state generation. Through simulation on synthetic Clifford+T workloads, the proposed scheduler achieves a normalized system speedup of 3.1x, improving over prior FTQC multiprogramming baselines by ~29% while maintaining low mean slowdown.