Quantum computing has the potential to transform modern computation by offering exponential advantages in areas such as cryptography, optimization, and intelligent data processing. To effectively realize these advantages, particularly in fault-tolerant and Noisy Intermediate-Scale Quantum (NISQ) environments, quantum circuits must be both resource-efficient and error-resilient. This paper presents a novel Binary-Coded Decimal (BCD) to Excess-3 code converter designed exclusively using the Clifford+T gate set, which is widely supported by fault-tolerant quantum hardware. The proposed design eliminates conventional 4-bit reversible adder-based implementations and instead employs an optimized logic structure based on Clifford+T-decomposed Peres gates. By leveraging Temporary Logical-AND gates and CNOT operations, the circuit achieves reduced T-count, circuit depth, and quantum cost as key metrics in fault-tolerant quantum computation. Functional correctness is verified through IBM Qiskit, Version 2.1 simulations for all valid BCD inputs. The proposed converter serves as a scalable and hardware-compatible arithmetic building block for resource-aware and AI-oriented quantum architectures.
Quantum computing has the potential to transform modern computation by offering exponential advantages in areas such as cryptography, optimization, and intelligent data processing. To effectively realize these advantages, particularly in fault-tolerant and Noisy Intermediate-Scale Quantum (NISQ) environments, quantum circuits must be both resource-efficient and error-resilient. This paper presents a novel Binary-Coded Decimal (BCD) to Excess-3 code converter designed exclusively using the Clifford+T gate set, which is widely supported by fault-tolerant quantum hardware. The proposed design eliminates conventional 4-bit reversible adder-based implementations and instead employs an optimized logic structure based on Clifford+T-decomposed Peres gates. By leveraging Temporary Logical-AND gates and CNOT operations, the circuit achieves reduced T-count, circuit depth, and quantum cost as key metrics in fault-tolerant quantum computation. Functional correctness is verified through IBM Qiskit, Version 2.1 simulations for all valid BCD inputs. The proposed converter serves as a scalable and hardware-compatible arithmetic building block for resource-aware and AI-oriented quantum architectures.
Within this paper, the authors introduce a new cost optimized quantum Binary-Coded Decimal (BCD) adder circuit that utilizes reversible gates as its building blocks. The newly proposed quantum BCD adder is specifically constructed with the inclusion of double Peres gates (DPG), Peres gates (PG), BJN gates, Feynman gates (FG), and reversible NOT gates. To bring this idea to life, we undertook the design and implementation of the proposed circuit using the Qiskit simulator provided by the IBM Quantum Computing lab. Our evaluation of the newly optimized BCD adder circuit yielded the following metrics, the quantum cost of 47, the constant input of 8, garbage output of 12, and a delay of 10. When compared to previously reported results, we observed significant improvements in various aspects, with a 25.39% reduction in quantum cost, a 28.57% decrease in constant input, and a 36.84% reduction in garbage output.
Abstract Fault-tolerant quantum neural networks (QNNs) require architectures that balance learning capability with stringent non-Clifford resource constraints. This work proposes an arithmetic-aware QNN architecture that integrates a validity-controlled binary-coded decimal (BCD)-to-Excess-3 transformation as a fault-tolerant preprocessing stage prior to variational learning. The arithmetic module is realized entirely within the Clifford+T gate set and incorporates explicit BCD validity detection, enabling conditional arithmetic execution while introducing only four additional T / T † gates beyond the underlying arithmetic core. The proposed architecture is combined with a COBYLA-optimized variational ansatz and compared against a baseline QNN of identical trainable complexity. While both models achieve identical classification accuracy of 100% on the benchmark single-digit task, the arithmetic-aware architecture demonstrates superior robustness under realistic hardware noise, achieving a robustness integral of 0.080 compared to 0.071 for the baseline model. Furthermore, curvature analysis reveals a substantially flatter optimization landscape, reducing the mean curvature from 36.85 to 27.21 and indicating that the arithmetic transformation acts as an effective inductive bias that stabilizes the learning process. To evaluate scalability, an additional four-class multi-digit (00–99) classification experiment was conducted, achieving an overall accuracy of 70%. These results demonstrate that fault-tolerant arithmetic preprocessing can enhance QNN robustness and stability while maintaining bounded non-Clifford overhead, highlighting the potential of arithmetic-aware representations for robust quantum machine learning.
Reversible logic is essential in quantum computing due to its ability to preserve information and establish a one-to-one mapping between inputs and outputs. The Clifford+T gate set, known for supporting fault-tolerant quantum circuits, offers resilience against decoherence but introduces high implementation costs, particularly due to the T gate's resource intensity. In this work, we propose a new and efficient quantum multiplexer design, the Quantum Clifford T-MUX, designed entirely within the Clifford+T framework. This multiplexer minimizes T-count and avoids the use of ancillary qubits, both critical factors for practical, fault-tolerant quantum computing. As part of this architecture, we present a newly designed fault-tolerant Peres gate using only Clifford+T gates, which serves as a fundamental building block in the T-MUX construction. The proposed T-MUX achieves reduced T-count, no garbage output, and improved efficiency compared to traditional designs. These improvements position it as a valuable component for building scalable quantum Arithmetic Logic Units (ALUs), data buses, and memory systems. Overall, this work contributes toward the development of low-overhead, modular quantum control structures suited for near-term and long-term quantum computing architectures. The proposed circuit is simulated using the Quirk online tool, and the result confirms the accuracy of the design. This design achieves an average 35% improvement in T-Count without any constant input, compared to its counterpart, respectively.
Reversible logic is characterized by its feature of being a prominent application in low-power conventional computers and the most compatible logic in quantum computers. Quantum circuits executes quantum algorithms and are important in a new generation of advanced computing. However, they are highly error-prone and also subject to the use of limited and sensitive physical resources like qubits and quantum gates. This paper introduces a comprehensive fault tolerant quantum-based reversible circuit which can calculate a high variety number of arithmetic and logic operations. It uses both: parity preserving method for detecting one or an odd number of bit errors, and Clifford + T implementation for protecting circuits against decoherence faults. First, we propose a new fault-tolerant (parity preserving and Clifford + T) adder/subtractor and derive a quantum reversible Arithmetic and Logic Unit (ALU). These modules reach the most optimized extent of circuit line, ancilla inputs, and garbage outputs according to the logical analysis done in this work. This article focuses on reducing T-cost metrics in conjunction with enhancing the number of operations and quantum costs in proposed circuits compared to other counterparts. We propose 4-bit fault tolerant ALU derived from our proposed single-bit module to show the proposed circuit can be extended to any larger size. The proposed circuit is implemented in the Qiskit simulation tool, and output results confirm the accuracy of our design functionality. The proposed full adder/ subtractor achieves an average of 64% and 43%, and the proposed ALU circuit achieves an average of 38% and 27% improvement in T-count and T-depth, respectively compared to their counterparts. The proposed reversible quantum-optimized fault tolerant adder/subtractor and ALU units can be applied as the basic part of DSP systems and quantum processor units in quantum computing devices.
Quantum Arithmetic Logic Units (ALUs) serve as critical components in quantum processors, enabling both arithmetic and logical operations on qubits. However, the fragile nature of quantum systems makes them susceptible to errors and decoherence, necessitating fault-tolerant designs. In this work, we propose a fault-tolerant quantum ALU architecture constructed using the Clifford+ T gate set, which is widely recognized for its compatibility with error-correcting codes. The proposed design minimizes quantum resource overhead while maintaining computational accuracy under fault-prone conditions. Notably, the architecture requires zero ancilla and generates a single garbage output, optimizing the qubit space. Performance evaluations demonstrate significant improvements, achieving a 31.8% reduction in T-count and a 33.3% reduction in T-depth compared to existing designs. These enhancements contribute to more efficient and reliable quantum computation, paving the way for scalable quantum processor development.
The quantum and reversible paradigm merges the principles of quantum mechanics and reversible computation to enable information-preserving processing. It supports next-generation computing architectures that provide improved scalability and enhanced computational efficiency. Within these architectures, the decimal adder is a key arithmetic component, particularly for Binary Coded Decimal (BCD) operations widely used in financial and commercial systems. However, most reversible BCD adders focus primarily on quantum and reversible metrics, overlooking the critical influence of delay, which makes balanced optimization a significant challenge. This paper presents two reversible BCD adder designs optimized for both delay and quantum cost. One design integrates the decimal carry-skip technique to improve the overall delay. Using reversible logic gates, the proposed architectures efficiently perform BCD addition and implement the required correction logic while maintaining full reversibility. Evaluation results indicate that the proposed designs surpass existing reversible BCD adders, achieving best-case average improvements of 85.12% in delay and 30.75% in quantum cost. These advancements demonstrate the potential of the proposed adders for integration into future quantum-based arithmetic units and scalable reversible computing systems. Moreover, analysis of real banking transaction data underscores the practical importance of BCD addition and its widespread use in accurate and efficient monetary computations.