This paper presents a CMOS-compatible Lechner-Hauke-Zoller (LHZ)--based analog tile structure as a fundamental unit for developing scalable analog Ising machines (IMs). In the designed LHZ tile, the voltage-controlled oscillators are employed as the physical Ising spins, while for the ancillary spins, we introduce an oscillator-based circuit to emulate the constraint needed to ensure the correct functionality of the tile. We implement the proposed LHZ tile in 12nm FinFET technology using the Cadence Virtuoso. Simulation results show the proposed tile could converge to the results in about 31~ns. Also, the designed spins could operate at approximately 13~GHz.
This paper presents a CMOS-compatible Lechner-Hauke-Zoller (LHZ)--based analog tile structure as a fundamental unit for developing scalable analog Ising machines (IMs). In the designed LHZ tile, the voltage-controlled oscillators are employed as the physical Ising spins, while for the ancillary spins, we introduce an oscillator-based circuit to emulate the constraint needed to ensure the correct functionality of the tile. We implement the proposed LHZ tile in 12nm FinFET technology using the Cadence Virtuoso. Simulation results show the proposed tile could converge to the results in about 31ns. Also, the designed spins could operate at approximately 13GHz.
Ising machines (IMs) have emerged as a promising solution for rapidly solving NP-complete combinatorial optimization problems, surpassing the capabilities of traditional computing methods. By efficiently determining the ground state of the Hamiltonian during the annealing process, IMs can effectively complement CPUs in tackling optimization challenges. To realize these IMs, a bistable oscillator is essential to emulate the atomic spins and interactions of the Ising model. This study introduces a Josephson parametric oscillator (JPO) based tile structure, serving as a fundamental unit for scalable superconductor-based IMs. Leveraging the bistable nature of JPOs, which are superconductor-based oscillators, the proposed machine can operate at frequencies of $\ensuremath{\sim}7.5$ GHz while consuming significantly less power (by three orders of magnitude) than complementary metal-oxide semiconductor based systems. Furthermore, the compatibility of the proposed tile structure with the Lechner-Hauke-Zoller architecture ensures its viability for large-scale integration. We conducted simulations of the tile in a noisy environment to validate its functionality. We verified its operational characteristics by comparing the results with the analytical solution of its Hamiltonian model. This verification demonstrates the feasibility and effectiveness of the JPO-based tile in implementing IMs, opening new avenues for efficient and scalable combinatorial optimization in quantum computing.
Complex combinatorial optimization problems serve as the foundation for various real-world applications. The time required to identify the optimal solutions to these problems escalates dramatically as the problem grows. Nevertheless, transforming these problems into another NP-complete problem, like the Ising model with a representation as a physical phenomenon, can be efficiently approximated. In this work, we use a system of bistable Josephson parametric oscillators (JPO) as artificial spins to realize the Ising model on a superconductor fabric. By integrating these JPOs based on the Lechner, Zoller, and Hauke (LHZ) architecture, we design a superconductor-based scalable Ising machine (IM). We develop a framework to automatically create the IM circuit and tune its parameters. The circuit functionality is assessed by simulating an IM designed for solving four-, six-, and ten-node unweighted Max-Cut problems.
In this work, we propose a novel methodology for on-chip control and readout circuits for the Lechner-Hauke-Zoller (LHZ) based superconductor Ising machines (IMs). By enabling the precise mapping of weight values on each spin realized by the Josephson parametric oscillator (JPO), we solve combinatorial optimization problems (COPs) efficiently. Our approach overcomes key challenges in mapping weighted Non-deterministic Polynomial Complete (NPC) problems. We demonstrate 3-bit weight resolution by dynamically modulating the phase of the pump current,Ipump, in JPOs using integrated control circuits. For the readout, we designed a Quasi One Junction SQUID (QOS) circuit capable of detecting 0 andπphase differences at the output of the JPOs. Finally, we validate our methodology by solving two weighted NPC problems by simulation.
With the growing demand for efficient computing to tackle complex real-world challenges like combinatorial optimization, both academia and industry are exploring alternative computing paradigms. The Ising machine (IM) is one such approach, solving optimization problems by mapping their cost functions onto the Ising model. In this framework, finding the optimal solution equates to determining the Ising spin configuration corresponding to the ground state of the Ising Hamiltonian. Analog IMs, relying on artificial spins that can take analogue rather than binary values, have shown great potential in reaching this ground at high speeds. Optical implementations, such as the opto-electronic IM developed within our research group, are particularly promising due to their higher bandwidth, energy efficiency, and lower latency compared to electronic IMs. However, scaling remains a challenge for large problems. To overcome this, we propose a novel analog optical IM utilizing a spatial light modulator (SLM). Our design differs from other IMs relying on SLMs by employing analog spin variables instead of binary ones and leveraging gradient descent-based feedback rather than a computer-driven Metropolis–Hastings sampling process. By exploiting the inherent parallelism of light, this SLM-based IM is expected to efficiently handle optimization problems with millions of spins while still maintaining high energy efficiency. At the conference, we will also offer more insight into the performance of these analogue IMs and will delve deeper in the bit resolution required for the different optical components such as the employed SLM. Based on the dynamical evolution of the IM, we will discuss strategies to further improve the problem-solving capacity and speed of these optical IMs.
Abstract Solving large-scale Quadratic Unconstrained Binary Optimization (QUBO) problems is critical in various fields, including finance, physics, biology and engineering. However, these problems remain intractable on conventional computing architectures. As a result, alternative solvers—such as Ising Machines (IMs) based on networks of coupled electronic, mechanical or photonic parametric oscillators (POs)—have recently been developed. PO-based Ising Machines (IMs) aim to find the ground state of an Ising Hamiltonian, which encodes the solution to a QUBO problem. However, they rely on an energy minimization process based on gradient descent, making them inherently susceptible to getting trapped in local minima and, as a result, to identifying inaccurate solutions. In this work, we introduce and validate a QUBO solver—the Analog Floquet Solver (AFS)—which enhances the dynamics of PO-based Ising machines (IMs) by leveraging Floquet states that emerge spontaneously in POs coupled to high quality-factor resonances. These states enable the AFS to embed periodic time modulation into its energy minimization process, allowing it to escape local minima during the search for QUBO problems’ solutions. As a result, the AFS significantly increases the likelihood of identifying accurate solutions compared to conventional PO-based IMs. More generally, this work establishes a new paradigm in analog computing that can be physically implemented using existing technologies across a variety of physical domains.
Unconventional computers based on superconducting qubits [1] and analog/digital hardware accelerators [2]–[5] have been developed and solved hard combinatorial optimization problems (COPs) with higher efficiency than classical computers by integrating the Ising models in hardware and observing their natural convergence behavior towards the lower Ising Hamiltonian (or energy). Ouantum annealer based on superconducting qubits [1] has demonstrated its capability of finding solutions to COPs using the quantum tunneling effect. However, the quantum computer requires operating at ultra-low temperatures (15-20mK), consumes excessive power (>10kW), and is not scalable yet to solve real-world problems. Recently, ASIC hardware accelerators [2]–[5] using low-cost CMOS technologies have implemented the Ising model by integrating many physical spins (i.e., computing units of the Ising model) to accelerate the finding of solutions to hard COPs. The hardware accelerators, so-called Ising machines, solved hard COPs much faster than classical computers and consumed several orders of magnitude lower energy. Nevertheless, they still have to overcome the fundamental scalability issues for solving large-scale COPs in the real world. The performance of existing discrete-time Ising machines has been limited by the exponentially increasing number of operation cycles when the problem size increases for the large-scale COPs. in addition, prior works have not been able to integrate massive random number generators (RNG), the essential building blocks of the Ising machines for finding better solutions, that could occupy a significant hardware footprint. Prior works have implemented them off-chip, or a few have been integrated on-chip and shared by many spins. This paper proposes a novel continuous-time analog Ising machine based on coupled inveiter chain circuits to address the scalability issues of the existing discrete-time Ising machines. Besides the benefits of the continuous-time operation, which significantly lowers the computing energy and latency, we introduce an equalization method for finding better solutions without RNGs.