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Custom Integrated Circuits Conference

A Continuous-Time Ising Machine using Coupled Inverter Chains Featuring Fully-Parallel One-Shot Spin Updates

Chengshuo Yu, Junjie Mu, Kevin Tshun Chuan Chai, Tony Kim, Bongjin Kim

Published Apr 1, 2023• 10 citations
Publisher

Abstract

Unconventional computers based on superconducting qubits [1] and analog/digital hardware accelerators [2]–[5] have been developed and solved hard combinatorial optimization problems (COPs) with higher efficiency than classical computers by integrating the Ising models in hardware and observing their natural convergence behavior towards the lower Ising Hamiltonian (or energy). Ouantum annealer based on superconducting qubits [1] has demonstrated its capability of finding solutions to COPs using the quantum tunneling effect. However, the quantum computer requires operating at ultra-low temperatures (15-20mK), consumes excessive power (>10kW), and is not scalable yet to solve real-world problems. Recently, ASIC hardware accelerators [2]–[5] using low-cost CMOS technologies have implemented the Ising model by integrating many physical spins (i.e., computing units of the Ising model) to accelerate the finding of solutions to hard COPs. The hardware accelerators, so-called Ising machines, solved hard COPs much faster than classical computers and consumed several orders of magnitude lower energy. Nevertheless, they still have to overcome the fundamental scalability issues for solving large-scale COPs in the real world. The performance of existing discrete-time Ising machines has been limited by the exponentially increasing number of operation cycles when the problem size increases for the large-scale COPs. in addition, prior works have not been able to integrate massive random number generators (RNG), the essential building blocks of the Ising machines for finding better solutions, that could occupy a significant hardware footprint. Prior works have implemented them off-chip, or a few have been integrated on-chip and shared by many spins. This paper proposes a novel continuous-time analog Ising machine based on coupled inveiter chain circuits to address the scalability issues of the existing discrete-time Ising machines. Besides the benefits of the continuous-time operation, which significantly lowers the computing energy and latency, we introduce an equalization method for finding better solutions without RNGs.

DOI
10.1109/cicc57935.2023.10121286

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Unconventional computers based on superconducting qubits [1] and analog/digital hardware accelerators [2]–[5] have been developed and solved hard combinatorial optimization problems (COPs) with higher efficiency than classical computers by integrating the Ising models in hardware and observing their natural convergence behavior towards the lower Ising Hamiltonian (or energy). Ouantum annealer based on superconducting qubits [1] has demonstrated its capability of finding solutions to COPs using the quantum tunneling effect. However, the quantum computer requires operating at ultra-low temperatures (15-20mK), consumes excessive power (>10kW), and is not scalable yet to solve real-world problems. Recently, ASIC hardware accelerators [2]–[5] using low-cost CMOS technologies have implemented the Ising model by integrating many physical spins (i.e., computing units of the Ising model) to accelerate the finding of solutions to hard COPs. The hardware accelerators, so-called Ising machines, solved hard COPs much faster than classical computers and consumed several orders of magnitude lower energy. Nevertheless, they still have to overcome the fundamental scalability issues for solving large-scale COPs in the real world. The performance of existing discrete-time Ising machines has been limited by the exponentially increasing number of operation cycles when the problem size increases for the large-scale COPs. in addition, prior works have not been able to integrate massive random number generators (RNG), the essential building blocks of the Ising machines for finding better solutions, that could occupy a significant hardware footprint. Prior works have implemented them off-chip, or a few have been integrated on-chip and shared by many spins. This paper proposes a novel continuous-time analog Ising machine based on coupled inveiter chain circuits to address the scalability issues of the existing discrete-time Ising machines. Besides the benefits of the continuous-time operation, which significantly lowers the computing energy and latency, we introduce an equalization method for finding better solutions without RNGs.
Although quantum computing is expected to supplant traditional computing in several application fields, its adoption is hampered by temperature and economic constraints. To overcome these hurdles, researchers have proposed complementary metal-oxide-semiconductor (CMOS) annealing circuits. These circuits draw inspiration from quantum computing algorithms such as quantum annealing and aim to achieve near-quantum benefits by leveraging traditional CMOS technologies. This paper introduces an Ising-model-based hardware architecture that can be applied to combinatorial optimization problems (COPs). With its ability to express quadratic unconstrained binary optimization (QUBO) formulations as polynomials, the Ising model facilitates the encapsulation of multiple solutions and mapping onto fully connected architecture. The proposed annealing accelerator utilizes traditional circuit technologies, including pseudo-random number generators (PRNGs), to realize the required algorithms. The chip proposed herein, implemented using Taiwan Semiconductor Manufacturing Company (TSMC) 90-nm CMOS technology, operates at 50 MHz and covers an area of $3.24{\mathrm{m}}{{\mathrm{m}}^2}$3.24mm2. Experimental results demonstrate the excellent performance of this annealing accelerator in terms of area and power consumption, indicating its promise for use in solving COPs rapidly.
Ising machines have received growing interest as efficient and hardware-friendly solvers for combinatorial optimization problems (COPs). They search for the absolute or approximate ground states of the Ising model with a proper annealing process. In contrast to Ising machines built with superconductive or optical circuits, complementary metal-oxide-semiconductor (CMOS) Ising machines offer inexpensive fabrication, high scalability, and easy integration with mainstream semiconductor chips. As low-energy and CMOS-compatible emerging technologies, spintronics and phase-transition devices offer functionalities that can enhance the scalability and sampling performance of Ising machines. In this article, we survey various approaches in the process flow for solving COPs using CMOS, hybrid CMOS-spintronic, and phase-transition devices. First, the methods for formulating COPs as Ising problems and embedding Ising formulations to the topology of the Ising machine are reviewed. Then, Ising machines are classified by their underlying operational principles and reviewed from a perspective of hardware implementation. CMOS solutions are advantageous with denser connectivity, whereas hybrid CMOS-spintronic and phase-transition device-based solutions show great potential in energy efficiency and high performance. Finally, the challenges and prospects are discussed for the Ising formulation, embedding process, and implementation of Ising machines.
Ising machines are hardware solvers which aim to find the absolute or approximate ground states of the Ising model. The Ising model is of fundamental computational interest because it is possible to formulate any problem in the complexity class NP as an Ising problem with only polynomial overhead. A scalable Ising machine that outperforms existing standard digital computers could have a huge impact for practical applications for a wide variety of optimization problems. In this review, we survey the current status of various approaches to constructing Ising machines and explain their underlying operational principles. The types of Ising machines considered here include classical thermal annealers based on technologies such as spintronics, optics, memristors, and digital hardware accelerators; dynamical-systems solvers implemented with optics and electronics; and superconducting-circuit quantum annealers. We compare and contrast their performance using standard metrics such as the ground-state success probability and time-to-solution, give their scaling relations with problem size, and discuss their strengths and weaknesses.
Combinatorial optimization problems are economically valuable but computationally hard to solve. Many practical combinatorial optimizations can be converted to the ground-state search problems of Ising spin models. Simulated bifurcation (SB) is a quantum-inspired algorithm to solve these Ising problems. One of the remarkable features of SB is the high-degree parallelism, providing an opportunity for quickly solving those problems by massively parallel processing. In this article, we review our recent works on the design and implementation of high-performance FPGA-based accelerators for SB and their applications toward innovative real-time systems that make optimal responses to ever-changing situations. An example of such an application is an ultrafast financial transaction machine that detects the most profitable cross-currency arbitrage opportunities at microsecond speeds. Also, we show a scale-out architecture for SB-based Ising machines with all-to-all spin-spin couplings that allows continued scaling of both machine size and computational throughput by connecting multiple chips, rather than scaling up a single chip.
Combinatorial optimization problems are economically valuable but computationally hard to solve. Many practical combinatorial optimizations can be converted to the ground-state search problems of Ising spin models. Simulated bifurcation (SB) is a quantum-inspired algorithm to solve these Ising problems. One of the remarkable features of SB is the high-degree parallelism, providing an opportunity for quickly solving those problems by massively parallel processing. In this article, we review our recent works on the design and implementation of high-performance FPGA-based accelerators for SB and their applications toward innovative real-time systems that make optimal responses to ever-changing situations. An example of such an application is an ultrafast financial transaction machine that detects the most profitable cross-currency arbitrage opportunities at microsecond speeds. Also, we show a scale-out architecture for SB-based Ising machines with all-to-all spin-spin couplings that allows continued scaling of both machine size and computational throughput by connecting multiple chips, rather than scaling up a single chip.
The Ising machine, as a quantum-inspired computing system, can be used to efficiently solve combinatorial optimization problems. Ongoing studies have positioned it to potentially surpass the performance limitations of traditional computers. However, such Ising machines also suffer from scalability as the solution quality becomes sub-optimal when the problem size increases. In this work, we propose an Ising-based framework that uses a distributed Ising algorithm to find the near-optimal solution for large-scale Max-Cut problems through parallel processing via graph segmentation and reassembly. We selected the coherent Ising machine as the hardware solver and successfully found the solution for a 2000-node instance utilizing 20 computational bits on the Gset standard dataset. Additionally, we investigated the key factors influencing the system's performance and discovered that setting the number of reorganizations to one results in higher accuracy. Building on this configuration, we utilized a 100-bit CIM hardware platform (CPQC-1) to solve instances with varying numbers of nodes. The experimental results agree well with the theoretical simulations, confirming the practical feasibility of our method. Moreover, compared to existing Ising-based solvers, our algorithm significantly reduces computational resource requirements while achieving superior performance on large-scale combinatorial optimization problems, highlighting its effectiveness on quantum-inspired hardware.