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IEEE Transactions on Nanotechnology

A Review of Ising Machines Implemented in Conventional and Emerging Technologies

Tingting Zhang, Qichao Tao, Bailiang Liu, Andrea Grimaldi, Eleonora Raimondo, Manuel Jiménez, M.J. Avedillo, Juan Núñez, B. Linares-Barranco, Teresa Serrano‐Gotarredona, Giovanni Finocchio, Jie Han

Published Jan 1, 2024• 32 citations
Publisher

Abstract

Ising machines have received growing interest as efficient and hardware-friendly solvers for combinatorial optimization problems (COPs). They search for the absolute or approximate ground states of the Ising model with a proper annealing process. In contrast to Ising machines built with superconductive or optical circuits, complementary metal-oxide-semiconductor (CMOS) Ising machines offer inexpensive fabrication, high scalability, and easy integration with mainstream semiconductor chips. As low-energy and CMOS-compatible emerging technologies, spintronics and phase-transition devices offer functionalities that can enhance the scalability and sampling performance of Ising machines. In this article, we survey various approaches in the process flow for solving COPs using CMOS, hybrid CMOS-spintronic, and phase-transition devices. First, the methods for formulating COPs as Ising problems and embedding Ising formulations to the topology of the Ising machine are reviewed. Then, Ising machines are classified by their underlying operational principles and reviewed from a perspective of hardware implementation. CMOS solutions are advantageous with denser connectivity, whereas hybrid CMOS-spintronic and phase-transition device-based solutions show great potential in energy efficiency and high performance. Finally, the challenges and prospects are discussed for the Ising formulation, embedding process, and implementation of Ising machines.

DOI
10.1109/tnano.2024.3457533

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Ising machines have received growing interest as efficient and hardware-friendly solvers for combinatorial optimization problems (COPs). They search for the absolute or approximate ground states of the Ising model with a proper annealing process. In contrast to Ising machines built with superconductive or optical circuits, complementary metal-oxide-semiconductor (CMOS) Ising machines offer inexpensive fabrication, high scalability, and easy integration with mainstream semiconductor chips. As low-energy and CMOS-compatible emerging technologies, spintronics and phase-transition devices offer functionalities that can enhance the scalability and sampling performance of Ising machines. In this article, we survey various approaches in the process flow for solving COPs using CMOS, hybrid CMOS-spintronic, and phase-transition devices. First, the methods for formulating COPs as Ising problems and embedding Ising formulations to the topology of the Ising machine are reviewed. Then, Ising machines are classified by their underlying operational principles and reviewed from a perspective of hardware implementation. CMOS solutions are advantageous with denser connectivity, whereas hybrid CMOS-spintronic and phase-transition device-based solutions show great potential in energy efficiency and high performance. Finally, the challenges and prospects are discussed for the Ising formulation, embedding process, and implementation of Ising machines.
Ising machines are hardware solvers which aim to find the absolute or approximate ground states of the Ising model. The Ising model is of fundamental computational interest because it is possible to formulate any problem in the complexity class NP as an Ising problem with only polynomial overhead. A scalable Ising machine that outperforms existing standard digital computers could have a huge impact for practical applications for a wide variety of optimization problems. In this review, we survey the current status of various approaches to constructing Ising machines and explain their underlying operational principles. The types of Ising machines considered here include classical thermal annealers based on technologies such as spintronics, optics, memristors, and digital hardware accelerators; dynamical-systems solvers implemented with optics and electronics; and superconducting-circuit quantum annealers. We compare and contrast their performance using standard metrics such as the ground-state success probability and time-to-solution, give their scaling relations with problem size, and discuss their strengths and weaknesses.
Combinatorial optimization problems are difficult to solve due to the space explosion in an exhaustive search. Using Ising model-based solvers can efficiently find near-optimal solutions by minimizing the energy of a nonlinear Hamiltonian system. In contrast to Ising machines based on quantum mechanics, classical Ising machines using conventional technologies, such as the complementary metal-oxide-semiconductor, offer efficient implementations with competitive performance. In this paper, we briefly review recently developed simulation algorithms of classical Ising machines. These algorithms are classified by considering various inherent mechanisms in the simulation of physical phenomena. Then, strategies to improve the simulation efficiency are discussed by generalizing their characteristics and behaviours. These simulation algorithms are key for improving the efficiency of classical Ising machines in solving combinatorial optimization problems.
Although quantum computing is expected to supplant traditional computing in several application fields, its adoption is hampered by temperature and economic constraints. To overcome these hurdles, researchers have proposed complementary metal-oxide-semiconductor (CMOS) annealing circuits. These circuits draw inspiration from quantum computing algorithms such as quantum annealing and aim to achieve near-quantum benefits by leveraging traditional CMOS technologies. This paper introduces an Ising-model-based hardware architecture that can be applied to combinatorial optimization problems (COPs). With its ability to express quadratic unconstrained binary optimization (QUBO) formulations as polynomials, the Ising model facilitates the encapsulation of multiple solutions and mapping onto fully connected architecture. The proposed annealing accelerator utilizes traditional circuit technologies, including pseudo-random number generators (PRNGs), to realize the required algorithms. The chip proposed herein, implemented using Taiwan Semiconductor Manufacturing Company (TSMC) 90-nm CMOS technology, operates at 50 MHz and covers an area of $3.24{\mathrm{m}}{{\mathrm{m}}^2}$3.24mm2. Experimental results demonstrate the excellent performance of this annealing accelerator in terms of area and power consumption, indicating its promise for use in solving COPs rapidly.
ABSTRACT Combinatorial optimization problems (COPs) are fundamental to numerous applications but remain challenging due to their exponentially large solution spaces and the limitations of conventional computing architectures. Ising machines have emerged as a promising alternative by mapping optimization problems onto the energy minimization of the Ising Hamiltonian. Various hardware implementations, including quantum annealers, digital annealers, and coherent Ising machines, have been explored based on distinct physical mechanisms. More recently, emerging device‐based approaches have gained significant attention for their potential to enable scalable and energy‐efficient optimization. In this review, we present a comprehensive overview of Ising machines from both theoretical and hardware perspectives, with particular emphasis on three emerging‐device‐based platforms: crossbar array‐based, stochastic p‐bit, and oscillator‐based Ising machines. We establish a comparative device‐to‐system perspective that traces how distinct physical and device properties translate into computational primitives, hardware architectures, and ultimately system‐level scalability. Platform‐specific bottlenecks, including array nonidealities and peripheral overhead in crossbar‐based systems, device variability and probability‐generation overhead in p‐bit systems, and synchronization and coupling‐network complexity in oscillator‐based systems, are quantitatively and qualitatively analyzed. Finally, we discuss future directions toward scalable and energy‐efficient Ising hardware through device‐to‐system co‐optimization across devices, circuits, architectures, and algorithms.
Combinatorial optimization problems with a large solution space are difficult to solve just using von Neumann computers. Ising machines or annealing machines have been developed to tackle these problems as a promising Non-von Neumann computer. In order to use these annealing machines, every combinatorial optimization problem is mapped onto the physical Ising model, which consists of spins, interactions between them, and their external magnetic fields. Then the annealing machines operate so as to search the ground state of the physical Ising model, which corresponds to the optimal solution of the original combinatorial optimization problem. A combinatorial optimization problem can be firstly described by an ideal fully-connected Ising model but it is very hard to embed it onto the physical Ising model topology of a particular annealing machine, which causes one of the largest issues in annealing machines. In this paper, we propose a fully-connected Ising model embedding method targeting for CMOS annealing machine. The key idea is that the proposed method replicates every logical spin in a fully-connected Ising model and embeds each logical spin onto the physical spins with the same chain length. Experimental results through an actual combinatorial problem show that the proposed method obtains spin embeddings superior to the conventional de facto standard method, in terms of the embedding time and the probability of obtaining a feasible solution.
Abstract Decades of exponential scaling in high-performance computing (HPC) efficiency is coming to an end. Transistor-based logic in complementary metal-oxide semiconductor (CMOS) technology is approaching physical limits beyond which further miniaturization will be impossible. Future HPC efficiency gains will necessarily rely on new technologies and paradigms of computing. The Ising model shows particular promise as a future framework for highly energy-efficient computation. Ising systems are able to operate at energies approaching thermodynamic limits for energy consumption of computation. Ising systems can function as both logic and memory. Thus, they have the potential to significantly reduce energy costs inherent to CMOS computing by eliminating costly data movement. The challenge in creating Ising-based hardware is in optimizing useful circuits that produce correct results on fundamentally nondeterministic hardware. The contribution of this paper is a novel machine learning approach, a combination of deep neural networks and random forests, for efficiently solving optimization problems that minimize sources of error in the Ising model. In addition, we provide a process to express a Boltzmann probability optimization problem as a supervised machine learning problem.