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arXiv:2309.03407 · Physical review. B./Physical review. B

Josephson parametric oscillator based Ising machine

Sasan Razmkhah, Mehdi Kamal, Nobuyuki Yoshikawa, Massoud Pedram

Published Jan 16, 2024• 11 citations
arXivHTMLPDF

Abstract

Ising machines (IMs) have emerged as a promising solution for rapidly solving NP-complete combinatorial optimization problems, surpassing the capabilities of traditional computing methods. By efficiently determining the ground state of the Hamiltonian during the annealing process, IMs can effectively complement CPUs in tackling optimization challenges. To realize these IMs, a bistable oscillator is essential to emulate the atomic spins and interactions of the Ising model. This study introduces a Josephson parametric oscillator (JPO) based tile structure, serving as a fundamental unit for scalable superconductor-based IMs. Leveraging the bistable nature of JPOs, which are superconductor-based oscillators, the proposed machine can operate at frequencies of $\ensuremath{\sim}7.5$ GHz while consuming significantly less power (by three orders of magnitude) than complementary metal-oxide semiconductor based systems. Furthermore, the compatibility of the proposed tile structure with the Lechner-Hauke-Zoller architecture ensures its viability for large-scale integration. We conducted simulations of the tile in a noisy environment to validate its functionality. We verified its operational characteristics by comparing the results with the analytical solution of its Hamiltonian model. This verification demonstrates the feasibility and effectiveness of the JPO-based tile in implementing IMs, opening new avenues for efficient and scalable combinatorial optimization in quantum computing.

DOI
10.1103/physrevb.109.014511

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Ising machines (IMs) have emerged as a promising solution for rapidly solving NP-complete combinatorial optimization problems, surpassing the capabilities of traditional computing methods. By efficiently determining the ground state of the Hamiltonian during the annealing process, IMs can effectively complement CPUs in tackling optimization challenges. To realize these IMs, a bistable oscillator is essential to emulate the atomic spins and interactions of the Ising model. This study introduces a Josephson parametric oscillator (JPO) based tile structure, serving as a fundamental unit for scalable superconductor-based IMs. Leveraging the bistable nature of JPOs, which are superconductor-based oscillators, the proposed machine can operate at frequencies of \ensuremath∼7.5\ensuremath{\sim}7.5\ensuremath∼7.5 GHz while consuming significantly less power (by three orders of magnitude) than complementary metal-oxide semiconductor based systems. Furthermore, the compatibility of the proposed tile structure with the Lechner-Hauke-Zoller architecture ensures its viability for large-scale integration. We conducted simulations of the tile in a noisy environment to validate its functionality. We verified its operational characteristics by comparing the results with the analytical solution of its Hamiltonian model. This verification demonstrates the feasibility and effectiveness of the JPO-based tile in implementing IMs, opening new avenues for efficient and scalable combinatorial optimization in quantum computing.
Complex combinatorial optimization problems serve as the foundation for various real-world applications. The time required to identify the optimal solutions to these problems escalates dramatically as the problem grows. Nevertheless, transforming these problems into another NP-complete problem, like the Ising model with a representation as a physical phenomenon, can be efficiently approximated. In this work, we use a system of bistable Josephson parametric oscillators (JPO) as artificial spins to realize the Ising model on a superconductor fabric. By integrating these JPOs based on the Lechner, Zoller, and Hauke (LHZ) architecture, we design a superconductor-based scalable Ising machine (IM). We develop a framework to automatically create the IM circuit and tune its parameters. The circuit functionality is assessed by simulating an IM designed for solving four-, six-, and ten-node unweighted Max-Cut problems.
This paper presents a CMOS-compatible Lechner-Hauke-Zoller (LHZ)--based analog tile structure as a fundamental unit for developing scalable analog Ising machines (IMs). In the designed LHZ tile, the voltage-controlled oscillators are employed as the physical Ising spins, while for the ancillary spins, we introduce an oscillator-based circuit to emulate the constraint needed to ensure the correct functionality of the tile. We implement the proposed LHZ tile in 12nm FinFET technology using the Cadence Virtuoso. Simulation results show the proposed tile could converge to the results in about 31~ns. Also, the designed spins could operate at approximately 13~GHz.
In this work, we propose a novel methodology for on-chip control and readout circuits for the Lechner-Hauke-Zoller (LHZ) based superconductor Ising machines (IMs). By enabling the precise mapping of weight values on each spin realized by the Josephson parametric oscillator (JPO), we solve combinatorial optimization problems (COPs) efficiently. Our approach overcomes key challenges in mapping weighted Non-deterministic Polynomial Complete (NPC) problems. We demonstrate 3-bit weight resolution by dynamically modulating the phase of the pump current,IpumpI_{pump}Ipump​, in JPOs using integrated control circuits. For the readout, we designed a Quasi One Junction SQUID (QOS) circuit capable of detecting 0 andπ\piπphase differences at the output of the JPOs. Finally, we validate our methodology by solving two weighted NPC problems by simulation.
Ising machines have received growing interest as efficient and hardware-friendly solvers for combinatorial optimization problems (COPs). They search for the absolute or approximate ground states of the Ising model with a proper annealing process. In contrast to Ising machines built with superconductive or optical circuits, complementary metal-oxide-semiconductor (CMOS) Ising machines offer inexpensive fabrication, high scalability, and easy integration with mainstream semiconductor chips. As low-energy and CMOS-compatible emerging technologies, spintronics and phase-transition devices offer functionalities that can enhance the scalability and sampling performance of Ising machines. In this article, we survey various approaches in the process flow for solving COPs using CMOS, hybrid CMOS-spintronic, and phase-transition devices. First, the methods for formulating COPs as Ising problems and embedding Ising formulations to the topology of the Ising machine are reviewed. Then, Ising machines are classified by their underlying operational principles and reviewed from a perspective of hardware implementation. CMOS solutions are advantageous with denser connectivity, whereas hybrid CMOS-spintronic and phase-transition device-based solutions show great potential in energy efficiency and high performance. Finally, the challenges and prospects are discussed for the Ising formulation, embedding process, and implementation of Ising machines.
We report on a new class of Ising machines (IMs) that rely on coupled parametric frequency dividers (PFDs) as macroscopic artificial spins. Unlike the IM counterparts based on subharmonic-injection locking (SHIL), PFD IMs do not require strong injected continuous-wave signals or applied dc voltages. Therefore, they show a significantly lower power consumption per spin compared to SHIL-based IMs, making it feasible to accurately solve large-scale combinatorial optimization problems that are hard or even impossible to solve by using the current von Neumann computing architectures. Furthermore, using high quality factor resonators in the PFD design makes PFD IMs able to exhibit a nanowatt-level power per spin. Also, it remarkably allows a speedup of the phase synchronization among the PFDs, resulting in shorter time to solution and lower energy to solution despite the resonators' longer relaxation time. As a proof of concept, a 4-node PFD IM has been demonstrated. This IM correctly solves a set of Max-Cut problems while consuming just 600 nanowatts per spin. This power consumption is 2 orders of magnitude lower than the power per spin of state-of-the-art SHIL-based IMs operating at the same frequency.
Although quantum computing is expected to supplant traditional computing in several application fields, its adoption is hampered by temperature and economic constraints. To overcome these hurdles, researchers have proposed complementary metal-oxide-semiconductor (CMOS) annealing circuits. These circuits draw inspiration from quantum computing algorithms such as quantum annealing and aim to achieve near-quantum benefits by leveraging traditional CMOS technologies. This paper introduces an Ising-model-based hardware architecture that can be applied to combinatorial optimization problems (COPs). With its ability to express quadratic unconstrained binary optimization (QUBO) formulations as polynomials, the Ising model facilitates the encapsulation of multiple solutions and mapping onto fully connected architecture. The proposed annealing accelerator utilizes traditional circuit technologies, including pseudo-random number generators (PRNGs), to realize the required algorithms. The chip proposed herein, implemented using Taiwan Semiconductor Manufacturing Company (TSMC) 90-nm CMOS technology, operates at 50 MHz and covers an area of $3.24{\mathrm{m}}{{\mathrm{m}}^2}$3.24mm2. Experimental results demonstrate the excellent performance of this annealing accelerator in terms of area and power consumption, indicating its promise for use in solving COPs rapidly.