Semiconductor quantum dot arrays are a promising platform to perform spin-based error-corrected quantum computation with large numbers of qubits. However, due to the diverging number of possible charge configurations combined with the limited sensitivity of large-footprint charge sensors, achieving single-spin occupancy in each dot in a growing quantum dot array is exceedingly complex. Therefore, to scale-up a spin-based architecture we must change how individual charges are readout and controlled. Here, we demonstrate single-spin occupancy of each dot in a foundry-fabricated array by combining two methods. 1/ Loading a finite number of electrons into the quantum dot array; simplifying electrostatic tuning by isolating the array from the reservoirs. 2/ Deploying multiplex gate-based reflectometry to dispersively probe charge tunneling and spin states without charge sensors or reservoirs. Our isolated arrays probed by embedded multiplex readout can be readily electrostatically tuned. They are thus a viable, scalable approach for spin-based quantum architectures. Large-footprint, low-sensitivity charge sensors hinder scaling semiconductor quantum dot arrays for quantum computation. Here the authors present a potentially scalable approach using multiplexed gate-based readout and operation in a foundry-fabricated quantum dot array, demonstrating single-electron occupancy.
Semiconductor quantum dot arrays are a promising platform to perform spin-based error-corrected quantum computation with large numbers of qubits. However, due to the diverging number of possible charge configurations combined with the limited sensitivity of large-footprint charge sensors, achieving single-spin occupancy in each dot in a growing quantum dot array is exceedingly complex. Therefore, to scale-up a spin-based architecture we must change how individual charges are readout and controlled. Here, we demonstrate single-spin occupancy of each dot in a foundry-fabricated array by combining two methods. 1/ Loading a finite number of electrons into the quantum dot array; simplifying electrostatic tuning by isolating the array from the reservoirs. 2/ Deploying multiplex gate-based reflectometry to dispersively probe charge tunneling and spin states without charge sensors or reservoirs. Our isolated arrays probed by embedded multiplex readout can be readily electrostatically tuned. They are thus a viable, scalable approach for spin-based quantum architectures. Large-footprint, low-sensitivity charge sensors hinder scaling semiconductor quantum dot arrays for quantum computation. Here the authors present a potentially scalable approach using multiplexed gate-based readout and operation in a foundry-fabricated quantum dot array, demonstrating single-electron occupancy.
Quantum computing is predicted to provide unprecedented enhancements in computational power. A quantum computer requires implementation of a well-defined and controlled quantum system of many interconnected qubits, each defined using fragile quantum states. The interest in a spin-based quantum computer in silicon stems from demonstrations of very long spin-coherence times, high-fidelity single spin control and compatibility with industrial mass-fabrication. Industrial scale fabrication of the silicon platform offers a clear route towards a large-scale quantum computer, however, some of the processes and techniques employed in qubit demonstrators are incompatible with a dense and foundry-fabricated architecture. In particular, spin-readout utilises external sensors that require nearly the same footprint as qubit devices. In this thesis, improved readout techniques for silicon quantum devices are presented and routes towards implementation of a scalable and high-sensitivity readout architecture are investigated. Firstly, readout sensitivity of compact gate-based sensors is improved using a high-quality factor resonator and Josephson parametric amplifier that are fabricated separately from quantum dots. Secondly, an integrated transistor-based control circuit is presented using which sequential readout of two quantum dot devices using the same gate-based sensor is achieved. Finally, a large-scale readout architecture based on random-access and frequency multiplexing is introduced. The impact of readout circuit footprint on readout sensitivity is determined, showing routes towards integration of conventional circuits with quantum devices in a dense architecture, and a fault-tolerant architecture based on mediated exchange is introduced, capable of relaxing the limitations on available control circuit footprint per qubit. Demonstrations are based on foundry-fabricated transistors and few-electron quantum dots, showing that industry fabrication is a viable route towards quantum computation at a scale large enough to begin addressing the most challenging computational problems.
There is currently a worldwide effort towards the realisation of large-scale quantum computers that exploit quantum phenomena for information processing. While these computing systems could potentially redefine the technological landscape, harnessing quantum effects is challenging due to their inherently fragile nature and the experimentally demanding environments in which they arise. In order for quantum computation to be viable it is first necessary to demonstrate the operation of two-level quantum systems (qubits) which have long coherence times, can be quickly read out, and can be controlled with high fidelity. Focusing on these key requirements, this thesis presents four experiments towards scalable solid state quantum computing using gate-defined quantum dot devices based on gallium arsenide (GaAs) heterostructures. The first experiment investigates a phonon emission process that limits the charge coherence in GaAs and potentially complicates the microwave control of multi-qubit devices. We show that this microwave analogy to Raman spectroscopy can provide a means of detecting the unique phonon spectral density created by a nanoscale device. Experimental results are compared to a theoretical model based on a non-Markovian master equation and approaches to suppressing electron-phonon coupling are discussed. The second experiment demonstrates a technique involving in-situ gate electrodes coupled to lumped-element resonators to provide high-bandwidth dispersive read-out of the state of a double quantum dot. We characterise the charge sensitivity of this method in the few-electron regime and benchmark its performance against quantum point contact charge sensors. The third experiment implements a low-loss, chip-level frequency multiplexing scheme for the readout of scaled-up spin qubit arrays. Dispersive gate-sensing is realised in combination with charge detection based on two radio frequency quantum point contacts to perform multiplexed readout of a double quantum dot in the few-electron regime. Demonstration of a 10-channel multiplexing device is achieved and limitations in scaling spin qubit readout to large numbers using multiplexed channels discussed. The final experiment ties previously presented results together by realising a micro-architecture for controlling and reading out qubits during the execution of a quantum algorithm. The basic principles of this architecture are demonstrated via the manipulation of a semiconductor qubit using control pulses that are cryogenically routed using a high-electron mobility transistor switching matrix controlled by a field programmable gate array. Finally, several technical results are also presented including the development of printed circuit board solutions to allow the high-frequency measurement of nanoscale devices at cryogenic temperatures and the design of on-chip interconnects used to suppress electromagnetic crosstalk in high-density spin qubit device architectures.
Silicon spin qubits are a promising platform for quantum computing due to their high coherence, controllability, and CMOS manufacturability, yet scalable implementations have so far been limited to a few qubits. Here, to take a step towards larger qubit systems, we tune and coherently control an eight-dot linear array of silicon spin qubits fabricated in a 300~mm CMOS-compatible foundry process, establishing operational scalability beyond the two-qubit regime. All eight qubits are successfully tuned and characterized as four double-dot pairs, exhibiting Ramsey dephasing times T2∗ up to 41(2)μs and Hahn-echo coherence times T2Hahn up to 1.31(4)ms. Readout of the central four qubits is achieved via a cascaded charge-sensing protocol, enabling high-fidelity measurements of the entire multi-qubit array in a two step process. Additionally, we demonstrate a two-qubit gate operation between adjacent qubits with low phase noise. We show that silicon spin qubit arrays can be scaled to medium-sized arrays of 8 qubits while maintaining system coherence.
With the progress made in advanced semiconductor manufacturing and in control and readout techniques, semiconductor based quantum computing has made significant progress in the past decade in both fidelities and coherence times. In view of scalability, an elementary computational unit that can retain key computational functionalities must be defined so that an array of such units can process information without excessive overhead. For quantum computation to proceed, not only should each qubit be able to perform operations in all dimensions about the Bloch sphere, but the detection of quantum states, either spin or charge, should also be fast, robust, and efficient. As the number of ancilla qubits needed for error correction scales with the number of computational qubits, there is a need for highly scalable, reproducible designs with a density sufficient to allow error correction. Finally, a cost-effective solution that maintains high compatibility with industry standards is needed to ensure industrialisation of such a unit. A compact arrangement eases scalability and allows a higher qubit density, while the versatility of such an architecture allows the circumvention of potentially defective or otherwise unusable portions of large-scale structures. This would allow minimising the footprint typically dedicated to error correction. This thesis proposes such an elementary unit in the form of a quadruple quantum-dot fabricated by a standard silicon-based Complementary metal- oxide-semiconductor (CMOS) process. Firstly, we show the flexibility of this device by reconfiguring the structure as a single-electron box (SEB) detector and as various double-quantum-dot (DQD) detector configurations. In all cases, we demonstrate a high fidelity fast readout exceeding 99.8% in 10µs. Finally, we discuss the ability for the DQD detector to exceed the performance of the SEB detector in an isolated quantum-dot array by thermalising with the lower temperature of T ≈42 ±2 mK as opposed to the electron temperature Te ≈139 ±4 mK.
Spin qubits based on semiconductor quantum dots are a promising prospect for quantum computation because of their high coherence times and gate fidelities. However, scaling up those structures to the numbers required by fault-tolerant quantum computing is currently hampered by a number of issues. One of the main issues is the need for single-shot low-footprint qubit readout. Here, we demonstrate the single-shot in situ measurement of a compact qubit unit-cell. The unit cell is composed of two electron spins with a controllable exchange interaction. We report initialization, single-shot readout and two-electron entangling gate. The unit cell was successfully operated at up to 1 K, with state-of-the-art charge noise levels extracted using free induction decay. With its integrated readout and high stability, this foundry fabricated qubit unit cell demonstrates strong potential for scalable quantum computing architectures.
Spin qubits in semiconductor quantum circuits have been identified as a compelling platform for large scale quantum computing. Today an ongoing effort of the community is aiming at the scaling of such systems by filling larger and larger arrays. In this context the development of tuning and readout protocols allowing to reduce the inherent complexity of such systems seems to be a necessity.In the first part of my thesis, I demonstrate array partitioning of a linear triple quantum dot defined in a AlGaAs/GaAs heterostructure via a highly tunable interdot tunnel coupling. This allows us to operate independently smaller sections of the array which reduces the number of available charge states for the system and therefore reduces its complexity during the tuning.The second part of my thesis is focused on reducing the hardware overhead necessary to extract information during the readout of the spin qubits. In semiconductor spin qubits, high fidelity read-out is obtained through Pauli spin blockade in a double quantum dot with two electrons probed by a local electrometer. One electron is the qubit, the second is the ancilla and only one bit of information is extracted. To obtain the full two-bit information of the two-electron spin states, more quantum hardware is necessary (either dots, electrometers, or reservoirs).Based on an original protocol, I develop in this thesis a complete single-shot read-out procedure for two-electron spin states in a double quantum dot discriminating between S, T0, T+ and T-. It uses successively three distinct spin-to-charge conversion protocols interleaved with charge configuration measurements. The strategy is based on four novel experimental achievements:First, the control from the GHz to sub-Hz regime of the interdot tunnel coupling at the nanosecond timescale.Second, the separation of the spin-to-charge conversion and the charge read-out in the voltage gate space.Third, the suppression of spin relaxation process during the read-out procedure.Finally, the repetition of three distinct spin-to-charge conversion protocols.The read-out procedure is tested on various initialized populations and implemented in more complex spin manipulation sequences to assess its validity.