Highly entangled quantum states are an ingredient in numerous applications in quantum computing. However, preparing these highly entangled quantum states on currently available quantum computers at high fidelity is limited by ubiquitous errors. Besides improving the underlying technology of a quantum computer, the scale and fidelity of these entangled states in near-term quantum computers can be improved by specialized compilation methods. In this work, the compilation of quantum circuits for the preparation of highly entangled architecture-specific graph states is addressed by defining and solving a formal model, i.e., a form of discrete constraint optimization. Our model incorporates information about gate cancellations, gate commutations, and accurate gate timing to determine an optimized graph state preparation circuit. Up to now, these aspects have only been considered independently of each other, typically applied to arbitrary quantum circuits. We quantify the quality of a generated state by performing stabilizer measurements and determining its fidelity. We show that our new method reduces the error when preparing a seven-qubit graph state by 3.5x on average compared to the state-of-the-art Qiskit solution. For a linear eight-qubit graph state, the error is reduced by 6.4x on average. The presented results highlight the ability of our approach to prepare higher fidelity or larger-scale graph states on gate-based quantum computing hardware.
Highly entangled quantum states are an ingredient in numerous applications in quantum computing. However, preparing these highly entangled quantum states on currently available quantum computers at high fidelity is limited by ubiquitous errors. Besides improving the underlying technology of a quantum computer, the scale and fidelity of these entangled states in near-term quantum computers can be improved by specialized compilation methods. In this work, the compilation of quantum circuits for the preparation of highly entangled architecture-specific graph states is addressed by defining and solving a formal model, i.e., a form of discrete constraint optimization. Our model incorporates information about gate cancellations, gate commutations, and accurate gate timing to determine an optimized graph state preparation circuit. Up to now, these aspects have only been considered independently of each other, typically applied to arbitrary quantum circuits. We quantify the quality of a generated state by performing stabilizer measurements and determining its fidelity. We show that our new method reduces the error when preparing a seven-qubit graph state by 3.5x on average compared to the state-of-the-art Qiskit solution. For a linear eight-qubit graph state, the error is reduced by 6.4x on average. The presented results highlight the ability of our approach to prepare higher fidelity or larger-scale graph states on gate-based quantum computing hardware.
Scalable quantum computing requires execution models that go beyond the capacity of a single quantum processing unit (QPU). Although current hardware platforms continue to increase in qubit count, large fault-tolerant applications require substantially more physical qubits, stronger connectivity, and lower effective error rates than a monolithic near-term device can provide. Multi-QPU and multi-core architectures therefore form an important route towards larger quantum systems. However, distributing a quantum computation introduces compiler and architecture constraints that do not arise in conventional classical distribution. A partitioned quantum circuit separates gates and qubits that may still be logically entangled or mutually dependent. The system must therefore provide quantum resources that support entanglement between the distributed circuit fragments, while each local subcircuit must remain executable on the hardware topology of its assigned QPU. In this thesis, graph states serve as the explicit interconnection resources for these nonlocal dependences: they encode the entanglement structure required to support teleportation-based operations across QPUs. This thesis studies scalable quantum execution as an architecture-driven compilation problem. It develops a staged framework in which distribution, graph-state-based interconnection, and interconnection robustness are treated as dependent compiler decisions. The framework addresses three connected questions: 1) how a large quantum circuit should be divided when the resulting subcircuits must match real QPU topologies; 2) how the graph states required to entangle and operate across the distributed circuit boundaries can be prepared efficiently on constrained hardware; and 3) how those graph-state resources can remain useful under the loss and fusion failures that arise during preparation and use. These questions define an execution path from a large logical circuit to distributed local workloads connected by explicit entanglement resources. The thesis makes three main technical contributions that instantiate this framework. 1) It introduces hardware-aware circuit cutting, which incorporates the relationship between subcircuit interaction graphs and target QPU topology into the partitioning objective. This stage produces distributed workloads and explicit cut boundaries where quantum entanglement must be supplied across QPUs. 2) It formulates graph-state preparation as the resource-generation stage for those boundaries and develops methods that reduce preparation depth and emitter usage by exploiting graph-state equivalence and divide-and-conquer construction. 3) It develops a robust graph-state interconnection scheme that uses tree-encoded fusion and spin-memory-assisted compilation to tolerate photon loss and probabilistic fusion failures, so that the graph state can serve as a reliable connection between distributed quantum program fragments.
The measurement-based architecture is a paradigm of quantum computing, relying on the entanglement of a cluster of qubits and the measurements of a subset of it, conditioning the state of the unmeasured output qubits. While methods to map the gate model circuits into the measurement-based are already available via intermediate steps, we introduce a paradigm for quantum compiling directly converting any quantum circuit to a class of graph states, independently from its size. This method relies on the stabilizer formalism to describe the register of the input qubits. An equivalence class between graph states able to implement the same circuit is defined, giving rise to a gauge freedom when compiling in the MBQC frame. The graph state can be rebuilt from the circuit and the input by employing a set of graphical rules. A system of equations describes the overall process. Compared with measurement calculus, the ancillary qubits are reduced by 50% on the quantum Fourier transform and 75% on the Quantum Approximate Optimization Algorithm, still preserving similar scaling laws for the number of entangling gates.
Abstract Quantum noise in real-world devices poses a significant challenge in achieving practical quantum advantage, since accurately compiled and executed circuits are typically deep and highly susceptible to decoherence. To facilitate the implementation of complex quantum algorithms on noisy hardware, we propose an approximate method for compiling target quantum circuits into brick-wall layouts. This new circuit design consists of two-qubit CNOT gates that can be directly implemented on real quantum computers, in conjunction with optimized one-qubit gates, to approximate the essential dynamics of the original circuit while significantly reducing its depth. Our approach is evaluated through numerical simulations of time-evolution circuits for the critical Ising model, quantum Fourier transformation, and Haar-random quantum circuits, as well as experiments on IBM quantum platforms. By accounting for compilation error and circuit noise, we demonstrate that time evolution and quantum Fourier transformation circuits achieve high compression rates, while random quantum circuits are less compressible. The degree of compression is related to the rate of entanglement accumulation in the target circuit. In particular, experiments on IBM platforms achieve a compression rate of 12.5 for N=12, significantly extending the application of current quantum devices. Furthermore, large-scale numerical simulations for system sizes up to N=30 reveal that the optimal depth dmax to achieve maximal overall fidelity is independent of system size N, suggesting the scalability of our method for large quantum devices in terms of quantum resources.
The design and benchmarking of quantum computer architectures traditionally rely on practical hardware restrictions, such as gate fidelities, control, and cooling. At the theoretical and software levels, numerous approaches have been proposed for benchmarking quantum devices, ranging from, , quantum volume to randomized benchmarking. In this work, we utilize the quantum information-theoretic properties of multipartite maximally entangled quantum states, in addition to their correspondence with quantum error-correction codes, permitting us to quantify the entanglement generated on near-term bilinear spin-qubit architectures. For this aim, we introduce four metrics that ascertain the quality of genuine multipartite quantum entanglement, along with circuit-level fidelity measures. As part of the task of executing a quantum circuit on a device, we devise simulations, which combine expected hardware characteristics of spin-qubit devices with appropriate compilation techniques; we then analyze three different architectural choices of varying lattice sizes for bilinear arrays, under three increasingly realistic noise models. We find that if the use of a compiler is assumed, sparsely connected spin-qubit lattices can approach comparable values of our metrics to those of the most highly connected device architecture. Even more surprisingly, by incorporating crosstalk into our last noise model, we find that, as error rates for crosstalk approach realistic values, the benefits of utilizing a bilinear array with advanced connectivity vanish. Our results highlight the limitations of adding local connectivity to near-term spin-qubit devices, and can be readily adapted to other qubit technologies. The framework developed here can be used for analyzing quantum entanglement on a device before fabrication, informing experimentalists on concomitant realistic expectations.
Quantum computing faces challenges such as noise, short coherence time, and limited qubit connections. These challenges worsen as quantum circuits become more complex. One major issue is the increasing depth of quantum circuits. This research proposes an optimization framework targeting depth and gate count reduction in quantum circuits, specifically for Noisy Intermediate-Scale Quantum (NISQ) devices. The proposed approach combines unitary merging of single-qubit gates, CNOT cancellation, gate commuting, and rotation gate rewriting strategies. Consecutive gates acting on the same qubit, such asRx(θ1)⋅Rx(θ2), are algebraically merged into a single rotation, while pairs of redundant CNOT gates are eliminated based on gate identity relations. The technique is implemented using Qiskit and validated across five diverse circuits including complex, random, and multi-qubit configurations. Experimental results show an average depth reduction of 33.33% and gate count reduction of 32.14%, with runtime improvement of up to 25%. For instance, an input circuit with a depth of 7 and gate count of 11 was reduced to a depth of 2 and 4 gates. All optimized circuits preserve functional correctness with a fidelityF≥0.99. High-resolution circuit diagrams are presented to visually demonstrate improvements before and after optimization. Additionally, global phase shifts such aseiπ/4are preserved or analytically characterized where relevant. This work enhances the viability of quantum computations on near-term hardware and opens pathways for future AI-driven quantum optimizations.
The Quantum Approximate Optimization Algorithm (QAOA) requires considered optimization problems to be translated into a compatible format. A popular transformation step in this pipeline involves the quadratization of higher-order binary optimization problems, translating them into Quadratic Unconstrained Binary Optimization (QUBO) formulations through the introduction of auxiliary variables. Conventional algorithms for the selection of auxiliary variables often aim to minimize the total number of required variables without taking the constraints of the underlying quantum computer-in particular, the connectivity of its qubits-into consideration. This quickly results in interaction graphs that are incompatible with the target device, resulting in a substantial compilation overhead even with highly optimized compilers. To address this issue, this work presents a novel approach for the selection of auxiliary variables tailored for architectures with limited connectivity. By specifically constructing an interaction graph with a regular structure and a limited maximal degree of vertices, we find a way to construct QAOA circuits that can be mapped efficiently to a variety of architectures. We show that, compared to circuits constructed from a QUBO formulation using conventional auxiliary selection methods, the proposed approach reduces the circuit depth by almost 40%. An implementation of all proposed methods is publicly available at https://github.com/munich-quantum-toolkit/problemsolver.