Error mitigation with stabilized noise in superconducting quantum processors
Young‐Seok Kim, Luke C. G. Govia, Andrew E. Dane, E. van den Berg, D. M. Zajac, Mitchell, Bradley, Yinyu Liu, Balakrishnan, Karthik, George Keefe, Adam Stabile, Emily Pritchett, J. Stehlik, Abhinav Kandala
Pre-fault tolerant quantum computers have already demonstrated the ability to estimate observable values accurately, at a scale beyond brute-force classical computation. This has been enabled by error mitigation techniques that often rely on a representative model on the device noise. However, learning and maintaining these models is complicated by fluctuations in the noise over unpredictable time scales, for instance, arising from resonant interactions between superconducting qubits and defect two-level systems (TLS). Such interactions affect the stability and uniformity of device performance as a whole, but also affect the noise model accuracy, leading to incorrect observable estimation. Here, we experimentally demonstrate that tuning of the qubit-TLS interactions helps reduce noise instabilities and consequently enables more reliable error-mitigation performance. These experiments provide a controlled platform for studying the performance of error mitigation in the presence of quasi-static noise. We anticipate that the capabilities introduced here will be crucial for the exploration of quantum applications on solid-state processors at non-trivial scales.
Pre-fault tolerant quantum computers have already demonstrated the ability to estimate observable values accurately, at a scale beyond brute-force classical computation. This has been enabled by error mitigation techniques that often rely on a representative model on the device noise. However, learning and maintaining these models is complicated by fluctuations in the noise over unpredictable time scales, for instance, arising from resonant interactions between superconducting qubits and defect two-level systems (TLS). Such interactions affect the stability and uniformity of device performance as a whole, but also affect the noise model accuracy, leading to incorrect observable estimation. Here, we experimentally demonstrate that tuning of the qubit-TLS interactions helps reduce noise instabilities and consequently enables more reliable error-mitigation performance. These experiments provide a controlled platform for studying the performance of error mitigation in the presence of quasi-static noise. We anticipate that the capabilities introduced here will be crucial for the exploration of quantum applications on solid-state processors at non-trivial scales.
Pre-fault tolerant quantum computers have already demonstrated the ability to estimate observable values accurately, at a scale beyond brute-force classical computation. This has been enabled by error mitigation techniques that often rely on a representative model of the device noise. However, learning and maintaining these models is complicated by fluctuations in the noise over unpredictable time scales, for instance, arising from resonant interactions between superconducting qubits and defect two-level systems (TLS). Such interactions affect the stability and uniformity of device performance as a whole, but also affect the noise model accuracy, leading to incorrect observable estimation. Here, we experimentally demonstrate that tuning of the qubit-TLS interactions helps reduce noise instabilities and consequently enables more reliable error-mitigation performance. These experiments provide a controlled platform for studying the performance of error mitigation in the presence of quasi-static noise. We anticipate that the capabilities introduced here will be crucial for the exploration of quantum applications on solid-state processors at non-trivial scales. Interactions between qubits and defect-related two-level systems in superconducting qubit devices are a major source of noise fluctuations that hinder error-mitigation performance. Here, the authors experimentally show that modulating this interaction can reduce noise fluctuation and improve error mitigation performance.
A long-standing challenge in quantum computing is developing technologies to overcome the inevitable noise in qubits. To enable meaningful applications in the early stages of fault-tolerant quantum computing, devising methods to suppress post-correction logical failures is becoming increasingly crucial. In this work, we propose and experimentally demonstrate the application of zero-noise extrapolation, a practical quantum error mitigation technique, to error correction circuits on superconducting processors. By amplifying the noise on physical qubits, the circuits yield outcomes that exhibit a predictable dependence on noise strength, following a polynomial function determined by the code distance. This property enables the effective application of polynomial extrapolation to mitigate logical errors. Our experiments demonstrate a universal reduction in logical errors across various quantum circuits, including fault-tolerant circuits of repetition and surface codes. We observe a favorable performance in multi-round error correction circuits, indicating that this method remains effective when the circuit depth increases. These results advance the frontier of quantum error suppression technologies, opening a practical way to achieve reliable quantum computing in the early fault-tolerant era. Quantum error mitigation refers to techniques that reduce, rather than correct, errors in quantum computing. Here the authors demonstrate zero-noise extrapolation applied to quantum error correction circuits on superconducting processors, effectively reducing logical errors and advancing early fault-tolerant quantum computing.
Abstract We present a method to improve the convergence of variational algorithms based on hidden inverses (HIs) to mitigate coherent errors. In the context of error mitigation, this means replacing the hardware implementation of certain Hermitian gates with their inverses. Doing so results in noise cancellation and a more resilient quantum circuit. This approach improves performance in a variety of two-qubit error models where the noise operator also inverts with the gate inversion. We apply the mitigation scheme on superconducting quantum processors running the variational quantum eigensolver (VQE) algorithm to find the H 2 ground-state energy. When implemented on superconducting hardware we find that the mitigation scheme effectively reduces the energy fluctuations in the parameter learning path in VQE, reducing the number of iterations for a converged value. We also provide a detailed numerical simulation of VQE performance under different noise models and explore how HIs and randomized compiling affect the underlying loss landscape of the learning problem. These simulations help explain our experimental hardware outcomes, helping to connect lower-level gate performance to application-specific behavior in contrast to metrics like fidelity which often do not provide an intuitive insight into observed high level performance.
Quantum computing promises to address problems in simulation, optimization, and chemistry, but current hardware operates in the noisy intermediate-scale (NISQ) regime where coherence limits, gate imperfections, and readout errors restrict performance. Improving calibration and mitigating errors therefore remain essential. This thesis analyzes error reduction on superconducting transmon qubits through calibration, gate analysis, and circuit-level mitigation. It compares single-qubit amplitude calibration methods and analyzes two-qubit gates based on the cross-resonance interaction, identifying differences in precision, convergence, and performance. In addition, it develops Inverted-Circuit Zero-Noise-Extrapolation (IC-ZNE) which measures effective error strength using inverted circuits. Compared to standard ZNE, IC-ZNE achieves results closer to ideal values and reduces observable errors. Overall, the presented methods improve the reliability of near-term quantum processors.
Quantum computing is entering a transitional regime between noisy intermediate-scale quantum (NISQ) processing and early fault-tolerant quantum computation (FTQC), in which increasingly capable hardware is beginning to support repeated syndrome measurements, partial error correction, and logical-qubit operations, while residual physical and logical errors remain non-negligible. In this regime, error suppression, error mitigation, and quantum error correction are increasingly better viewed as complementary layers of a unified error-reduction strategy rather than as separate approaches, with each acting at a different stage of the quantum computation to improve simulation reliability. Thus, in this review, we provide a practical and forward-looking overview of the principal hardware error sources and the corresponding error suppression and mitigation methods for reducing their impact across the current NISQ-FTQC transition. We discuss hardware-aware circuit design, coherent-error suppression, readout mitigation, noise extrapolation, classical inference, and software-supported workflows, with particular emphasis on their implementation on actual quantum processors. We further examine how error mitigation techniques can be adapted to encoded and logical-qubit settings so that they can operate alongside quantum error correction to suppress residual logical errors and improve the accuracy of computation in the early fault-tolerant regime.
Error-free computation is an unattainable ideal, yet our world now contains many computers that appear error-free to their users. That such things are possible is explained by sophisticated theorems that demonstrate the possibility of efficiently reducing computational errors introduced by reasonably well-behaved noise. My thesis is about the problem of determining whether noise in prototype quantum information processors is sufficiently well-behaved for fault-tolerant quantum computing to be possible. My work is divided into two themes. The first theme is the interpretation of average gate fidelity, a quantity that has become the standard performance metric for assessing progress towards fault tolerance. I have elucidated the connection between average gate fidelity and the requirements of fault-tolerant quantum computing by demonstrating the limits of fidelity as a proxy for error rate, the usual metric in fault-tolerance literature. I thereby conclude that information additional to fidelity is required to assess progress towards fault-tolerance. The second theme is the characterization of two-level defect systems, a particularly deleterious kind of noise that can affect superconducting-integrated-circuit-based quantum computing prototypes. I have designed statistical experimental design algorithms that can rigorously assess the influence of these defect systems, and I helped develop a proposal to mitigate their influence. I thereby demonstrate that existing experimental techniques can become much more powerful by employing advanced data collection procedures. My work has immediate implications for current research efforts towards the first working quantum computer. Theoretical work should be directed at assessing noise sources using metrics other than average gate fidelity, and future experimental characterization techniques should become more modular in order to incorporate advanced statistical inference techniques like the ones I develop herein.