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arXiv:2405.08982 · ACM/IEEE Design Automation Conference (DAC)

Efficient and Scalable Architectures for Multi-level Superconducting Qubit Readout

Chaithanya Naik Mude, Satvik Maurya, Benjamin Lienhard, Swamit Tannu

Published Jun 22, 2025• 2 citations
arXivHTMLPDF

Abstract

Realizing the full potential of quantum computing requires large-scale quantum computers capable of running quantum error correction (QEC) to mitigate hardware errors and maintain quantum data coherence. While quantum computers operate within a two-level computational subspace, many processor modalities are inherently multi-level systems. This leads to occasional leakage into energy levels outside the computational subspace, complicating error detection and undermining QEC protocols. The problem is particularly severe in engineered qubit devices like superconducting transmons, a leading technology for fault-tolerant quantum computing. Addressing this challenge requires effective multi-level quantum system readout to identify and mitigate leakage errors. We propose a scalable, high-fidelity three-level readout that reduces FPGA resource usage by $60 \times$ compared to the baseline while reducing readout time by $20 \%$, enabling faster leakage detection. By employing matched filters to detect relaxation and excitation error patterns and integrating a modular lightweight neural network to correct crosstalk errors, the protocol significantly reduces hardware complexity, achieving a $100 \times$ reduction in neural network size. Our design supports efficient, real-time implementation on off-the-shelf FPGAs, delivering a $6.6 \%$ relative improvement in readout accuracy over the baseline. This innovation enables faster leakage mitigation, enhances QEC reliability, and accelerates the path toward faulttolerant quantum computing.

DOI
10.1109/dac63849.2025.11133314

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Realizing the full potential of quantum computing requires large-scale quantum computers capable of running quantum error correction (QEC) to mitigate hardware errors and maintain quantum data coherence. While quantum computers operate within a two-level computational subspace, many processor modalities are inherently multi-level systems. This leads to occasional leakage into energy levels outside the computational subspace, complicating error detection and undermining QEC protocols. The problem is particularly severe in engineered qubit devices like superconducting transmons, a leading technology for fault-tolerant quantum computing. Addressing this challenge requires effective multi-level quantum system readout to identify and mitigate leakage errors. We propose a scalable, high-fidelity three-level readout that reduces FPGA resource usage by 60×60 \times60× compared to the baseline while reducing readout time by 20%20 \%20%, enabling faster leakage detection. By employing matched filters to detect relaxation and excitation error patterns and integrating a modular lightweight neural network to correct crosstalk errors, the protocol significantly reduces hardware complexity, achieving a 100×100 \times100× reduction in neural network size. Our design supports efficient, real-time implementation on off-the-shelf FPGAs, delivering a 6.6%6.6 \%6.6% relative improvement in readout accuracy over the baseline. This innovation enables faster leakage mitigation, enhances QEC reliability, and accelerates the path toward faulttolerant quantum computing.
Reliable qubit readout is a critical bottleneck toward fault-tolerant quantum computing (FTQC). In superconducting quantum processors, readout operations are both error-prone and high-latency. These challenges become more severe in frequency-multiplexed architectures, where signal crosstalk among neighboring qubits significantly degrades readout fidelity. Existing machine learning (ML)-based approaches rely on feed-forward neural networks (FNNs) that suffer from large parameter sizes and lack an end-to-end network that jointly addresses relaxation errors and discriminates qubit states. In this work, we present a multi-stage qubit state discriminator based on the Mamba model, which enables efficient sequence modeling with linear complexity. The first stage performs initial state discrimination, followed by a refinement stage that identifies and mitigates relaxation-induced errors. Our lightweight model achieves a geometric mean readout fidelity of 0.906, outperforming the best-reported state-of-the-art method while reducing parameter size by 49.6%; our optimal model further reaches 0.911. Both models remain robust across varying input trace lengths, maintaining a high fidelity of 0.893 at readout durations as short as 500 nsnsns, achieving up to a 26% reduction in logical error rate over prior work in quantum error correction (QEC).
The realization of fault-tolerant quantum computing requires the execution of quantum error-correction (QEC) schemes, to mitigate the fragile nature of qubits. In this context, to ensure the success of QEC, a protocol capable of implementing both qubit reset and leakage reduction is highly desirable together with the ability to perform fast and high-fidelity readout of the qubit s’ quantum states. In this thesis, we tackle both these challenges in an architecture consisting of fixed-frequency transmon qubits pair-wise coupled via tunable couplers. We demonstrate a readout scheme that combines two microwave techniques: applying a shelving technique to the qubits that reduces the contribution of decay error during readout, and a two-tone excitation of the readout resonators to distinguish among qubits’ populations in higher energy levels. We perform single-shot frequency-multiplexed qubit readout, with a 140 ns readout time, and demonstrate 99.5% assignment fidelity for two-state readout and 96.9% for three-state readout - without using a quantum-limited amplifier. We also demonstrate a reset scheme that is fast, unconditional, and achieves fidelities well above 99%, thus enabling fixed-frequency qubit architectures as future implementations of fault-tolerant quantum computers. Our reset protocol uses the tunable couplers to transfer any undesired qubits’ excitation to the readout resonators of the qubits, from which this excitation decays into the feedline. In total, the combination of qubit reset, leakage reduction, and coupler reset takes only 83 ns to complete. This reset protocol also provides a means to both reduce QEC cycle runtime and improve algorithmic fidelity on quantum processors.
Quantum error correction (QEC) is essential for achieving low error rates required for fault-tolerant quantum computation. In stabilizer-based codes such as the surface code, errors are inferred from repeated syndrome measurements and corrected by a classical decoder. To prevent error accumulation, decoding must be performed with both high throughput and low latency to keep pace with the QEC cycle and enable real-time feedback for universal logical operations. Here we report a hardware-integrated control architecture featuring an FPGA-based neural-network (NN) decoder and experimentally demonstrate real-time surface-code (distance-3) QEC on a superconducting quantum processor. The system achieves a deterministic closed-loop latency of 550 ns, including 124 ns for NN decoding, enabling feedback corrections within a 1.25 us QEC cycle. We show that real-time decoding and feedback correction achieve logical performance comparable to offline decoding while maintaining robustness against varying error conditions. We further demonstrate mid-circuit feedback correction in non-Clifford logical circuits, where Pauli-frame updating alone becomes insufficient. Our results establish a low-latency hardware architecture for embedded QEC control and provide a pathway towards scalable fault-tolerant quantum computing systems.
Superconducting qubits are a promising platform for building fault-tolerant quantum computers, with recent achievement showing the suppression of logical error with increasing code size. However, leakage into noncomputational states, a common issue in practical quantum systems including superconducting circuits, introduces correlated errors that undermine quantum error correction (QEC) scalability. Here, we propose and demonstrate a leakage reduction scheme utilizing tunable couplers, a widely adopted ingredient in large-scale superconducting quantum processors. Leveraging the strong frequency tunability of the couplers and stray interaction between the couplers and readout resonators, we eliminate state leakage on the couplers, thus suppressing space-correlated errors caused by population propagation among the couplers. Assisted by the couplers, we further reduce leakage to higher qubit levels with high efficiency (98.1%) and low error rate on the computational subspace (0.58%), suppressing time-correlated errors during QEC cycles. The performance of our scheme demonstrates its potential as an indispensable building block for scalable QEC with superconducting qubits.
Without increasing decoding delay, fault-tolerant quantum processing must lessen the effects of physical noise, measurement errors, leakage errors, and correlated disturbances. A multi-level quantum error correcting architecture for scalable quantum processors is examined in this research. Physical-layer syndrome extraction, logical-layer stabilizer decoding, and architecture-level error propagation control are the three types of correction. To balance the dependability of local rectification with global logical consistency, a comparatively compact noise-aware decoding technique has been presented. According to simulation data, the suggested architecture has enhanced robustness to correlated noise by 31.8%, decreased the average decoding delay by 24.3%, and reduced the logical error rate by 37.6% when compared to a single-level surface-code baseline. According to the findings, the hierarchical correction approach offers a suitable trade-off between accuracy and resource usage for real-time decoding. For large-scale quantum computing systems, the paper offers an engineering-focused correction model that simultaneously takes decoder responsiveness, qubit layout, and logical fidelity into account.
Quantum computers will require quantum error correction to reach the low error rates necessary for solving problems that surpass the capabilities of conventional computers. One of the dominant errors limiting the performance of quantum error correction codes across multiple technology platforms is leakage out of the computational subspace arising from the multilevel structure of qubit implementations. Here, we present a resource-efficient universal leakage reduction unit for superconducting qubits using parametric flux modulation. This operation removes leakage down to our measurement inaccuracy of 7×10^{-4} in approximately 50 ns with a low error of 2.5(1)×10^{-3} on the computational subspace, thereby reaching durations and fidelities comparable to those of single-qubit gates. We demonstrate that using the leakage reduction unit in repeated weight-two stabilizer measurements reduces the total number of detected errors in a scalable fashion to close to what can be achieved using leakage-rejection methods that do not scale. Our approach does not require additional control electronics or on-chip components and is applicable to both auxiliary and data qubits. These benefits make our method particularly attractive for mitigating leakage in large-scale quantum error correction circuits, a crucial requirement for the practical implementation of fault-tolerant quantum computation.