Abstract Ever since the discussions about a possible quantum computer arised, quantum simulations have been at the forefront of possible utilities, with the task of quantum simulations being one that promises quantum advantage. Recently, advancements have made it feasible to simulate complex molecules using Variational Quantum Eigensolvers or study the dynamics of many‐body spin Hamiltonians. These simulations have the potential to yield valuable outcomes through the application of error mitigation techniques. Simulating smaller models carries a great amount of importance as well and currently, in the Noisy Intermediate Scale Quantum era, is more feasible since it is less prone to errors. The objective of this work is to examine the theoretical background and the circuit implementation of a quantum tunneling simulation, with an emphasis on hardware considerations. This study presents the theoretical background required for such implementation and highlights the main stages of its development. By building on classic approaches of quantum tunneling simulations, this study aims at improving the result of such simulations by employing error mitigation techniques, Zero Noise Extrapolation, and Readout Error Mitigation and uses them in conjunction with multiprogramming of the quantum chip, a technique used for solving the hardware under‐utilization problem that arises in such contexts.
Abstract Ever since the discussions about a possible quantum computer arised, quantum simulations have been at the forefront of possible utilities, with the task of quantum simulations being one that promises quantum advantage. Recently, advancements have made it feasible to simulate complex molecules using Variational Quantum Eigensolvers or study the dynamics of many‐body spin Hamiltonians. These simulations have the potential to yield valuable outcomes through the application of error mitigation techniques. Simulating smaller models carries a great amount of importance as well and currently, in the Noisy Intermediate Scale Quantum era, is more feasible since it is less prone to errors. The objective of this work is to examine the theoretical background and the circuit implementation of a quantum tunneling simulation, with an emphasis on hardware considerations. This study presents the theoretical background required for such implementation and highlights the main stages of its development. By building on classic approaches of quantum tunneling simulations, this study aims at improving the result of such simulations by employing error mitigation techniques, Zero Noise Extrapolation, and Readout Error Mitigation and uses them in conjunction with multiprogramming of the quantum chip, a technique used for solving the hardware under‐utilization problem that arises in such contexts.
In the past few years, the first commercially available quantum computers have emerged, in an early stage of development, the so-called Noisy Intermediate-Scale Quantum (NISQ) era. Although these devices are still very prone to errors of different natures, they also have shown to deal successfully with small computational problems. Nowadays, one of the challenges in quantum computation is exactly to be able to show that quantum computers are useful, whereby mitigating the effects of the faulty hardware is pivotal. Recently, a wide range of quantum error mitigation techniques have been proposed and successfully implemented, alternative to quantum error correction codes. Herein, we discuss several types of noise in a quantum computer and techniques available to mitigate them, as well as their limitations and conditions of applicability. We also suggest an hierarchy for them, towards the conception of a layered software framework of error mitigation techniques, and implement some of them in a quantum simulation of the Heisenberg model on an IBM quantum computer, improving the fidelity of the simulation by 2.8x.
Quantum computing is entering a transitional regime between noisy intermediate-scale quantum (NISQ) processing and early fault-tolerant quantum computation (FTQC), in which increasingly capable hardware is beginning to support repeated syndrome measurements, partial error correction, and logical-qubit operations, while residual physical and logical errors remain non-negligible. In this regime, error suppression, error mitigation, and quantum error correction are increasingly better viewed as complementary layers of a unified error-reduction strategy rather than as separate approaches, with each acting at a different stage of the quantum computation to improve simulation reliability. Thus, in this review, we provide a practical and forward-looking overview of the principal hardware error sources and the corresponding error suppression and mitigation methods for reducing their impact across the current NISQ-FTQC transition. We discuss hardware-aware circuit design, coherent-error suppression, readout mitigation, noise extrapolation, classical inference, and software-supported workflows, with particular emphasis on their implementation on actual quantum processors. We further examine how error mitigation techniques can be adapted to encoded and logical-qubit settings so that they can operate alongside quantum error correction to suppress residual logical errors and improve the accuracy of computation in the early fault-tolerant regime.
We explore the field of quantum computing and specifically address the crucial problem of error reduction in the context of IBM simulators. Although quantum computing is a rapidly developing technology with great potential, its practical applications are severely hindered by its inherent error-proneness. We tackle this problem by introducing new developments in quantum error correction techniques designed for IBM simulators. In contrast to conventional methods that frequently depend on large matrices or pre-established error models; our technique presents a flexible and dynamic approach. By utilizing several variations of a main circuit, in which classically efficient gates are used in place of non-Clifford gates, we are able to discover the best compensation scheme from scratch for actual quantum systems. The suggested method exhibits great flexibility in handling different levels of noise and different kinds of noise, such as spatially and temporally correlated variations. It also effectively reduces errors on IBM quantum hardware as well as precisely emulated imperfect quantum computers. By offering a thorough investigation of sophisticated error mitigation techniques, this research advances the continuing quest for dependable quantum computations and opens up interesting new directions for improving both the accuracy and performance of quantum computing operations carried out on IBM simulators.
In this perspective article, we revisit and critically evaluate prevailing viewpoints on the capabilities and limitations of near-term quantum computing and its potential transition toward fully fault-tolerant quantum computing. We examine theoretical no-go results and their implications, addressing misconceptions about the practicality of quantum error mitigation techniques and variational quantum algorithms. By emphasizing the nuances of error scaling, circuit depth, and algorithmic feasibility, we highlight viable near-term applications and synergies between error mitigation and early fault-tolerant architectures. Our discussion explores strategies for addressing current challenges, such as barren plateaus in variational circuits and the integration of quantum error mitigation and quantum error correction techniques. We aim to underscore the importance of continued innovation in hardware and algorithmic design to bridge the gap between theoretical potential and practical utility, paving the way for meaningful quantum advantage in the era of late noisy intermediate scale and early fault-tolerant quantum devices.
Analog quantum simulation has been proposed as an efficient approach for
probing classically intractable many-body physics. In contrast to digital,
gate-based quantum simulation, the analog approach involves configuring the
quantum hardware to directly mimic the physics of the target system. This
reduces the level of control required and can offer a degree of inherent
robustness, but it comes at the cost that known error-handling techniques may
be inapplicable. Accumulation of error is thus a major challenge facing
medium-scale and large-scale analog quantum simulation with current and
near-term noisy quantum (NISQ) devices. Here we propose a hybrid error
mitigation scheme that can suppress general local Markovian noise in analog
quantum simulators. We employ stochastic error mitigation for physical noise
and use Richardson extrapolation to compensate for model estimation error. We
numerically test the error mitigation scheme for an Ising-type Hamiltonian with
energy relaxation and dephasing noise, and show an improvement of simulation
accuracy by two orders. We assess the resource cost of our error mitigation
scheme and conclude that analog quantum simulation at scale is feasible with
NISQ hardware.
Quantum computing holds the potential to address problems that are currently considered intractable for classical processors by leveraging quantum mechanical effects for simulation, optimization, and chemistry. Despite recent technological progress, quantum hardware remains in the noisy intermediate-scale regime, where coherence limits, gate imperfections, and readout errors restrict circuit depth and algorithmic reliability. Although first demonstrations of small-scale Quantum Error Correction exist, logical processors with low logical error rates are still distant. In the near term, even error-corrected qubits are expected to operate with residual error, which means that improving calibration and mitigating errors at the physical and circuit level will remain essential for obtaining meaningful results. Established calibration routines and mitigation methods such as Zero-Noise-Extrapolation (ZNE) are valuable, but need to be further improved and more rigorously validated with respect to their underlying assumptions, stability and quantitative benefits. This thesis addresses error reduction techniques on transmon qubits through calibration, gate analysis, and circuit-level mitigation. First, a systematic comparison of two single-qubit amplitude calibration techniques is carried out (cross-point and ping-pong calibration), followed by an analysis of two implementations of a two-qubit gate, based on the cross-resonance interaction. The results show that cross-point calibration offers faster convergence, higher precision and a more favorable signal to noise ratio than ping-pong calibration. Hamiltonian tomography confirms the validity of a reduced model for the cross-resonance interaction, and algorithmic tests reveal that direct and echoed CNOT gates offer complementary advantages depending on the application. Second, the thesis develops and evaluates the method of Inverted-Circuit Zero-Noise-Extrapolation (IC-ZNE). Its main idea consists of measuring the effective error strength of a circuit through inverted circuits. This quantity is then used for extrapolation towards zero noise rather than relying on simple, approximate noise scaling assumptions as in standard ZNE. This approach constitutes a novel and original method. IC-ZNE consistently produces results closer to ideal reference values than standard ZNE. The method achieves up to 77% error reduction in observable error on the tested circuits compared to standard ZNE and simple post processing filters can yield up to 39% reduction in selected cases compared to standard ZNE. Further refinements introduce noise-adaptive circuit scaling strategies that enhance mitigation outcomes without significant additional cost. The performance of these techniques is examined across several circuits and in the context of variational quantum algorithms. Applications to the Quantum Approximate Optimization Algorithm and the Variational Quantum Eigensolver demonstrate that these techniques extend the useful operating regime of current devices, although their effectiveness decreases for very deep circuits or unfavorable variational ansätze. Taken together, the calibration and mitigation techniques investigated and developed in this thesis demonstrate practical routes toward enhancing the reliability of near-term quantum processors. While they cannot replace full fault-tolerant quantum computation, they offer useful and complementary capabilities that support progress toward scalable quantum technologies.