It is well understood that a two-dimensional grid of locally interacting qubits is a promising platform for achieving fault-tolerant quantum computing. However in the near future, it may prove less challenging to develop lower-dimensional structures. In this paper, we show that such constrained architectures can also support fault tolerance; specifically we explore a 2 × N array of qubits where the interactions between non-neighboring qubits are enabled by shuttling the logical information along the rows of the array. Despite the apparent constraints of this setup, we demonstrate that error correction is possible and identify the classes of codes that are naturally suited to this platform. Focusing on silicon spin qubits as a practical example of qubits believed to meet our requirements, we provide a protocol for achieving full universal quantum computation with the surface code, while also addressing the additional constraints that are specific to a silicon spin-qubit device. Through numerical simulations, we evaluate the performance of this architecture using a realistic noise model, demonstrating that both surface code and more complex quantum low-density parity-check codes efficiently suppress gate and shuttling noise to a level that allows for the execution of quantum algorithms within the classically intractable regime. This work thus brings us one step closer to the execution of quantum algorithms that outperform classical machines. Published by the American Physical Society 2024
It is well understood that a two-dimensional grid of locally interacting qubits is a promising platform for achieving fault-tolerant quantum computing. However in the near future, it may prove less challenging to develop lower-dimensional structures. In this paper, we show that such constrained architectures can also support fault tolerance; specifically we explore a 2 × N array of qubits where the interactions between non-neighboring qubits are enabled by shuttling the logical information along the rows of the array. Despite the apparent constraints of this setup, we demonstrate that error correction is possible and identify the classes of codes that are naturally suited to this platform. Focusing on silicon spin qubits as a practical example of qubits believed to meet our requirements, we provide a protocol for achieving full universal quantum computation with the surface code, while also addressing the additional constraints that are specific to a silicon spin-qubit device. Through numerical simulations, we evaluate the performance of this architecture using a realistic noise model, demonstrating that both surface code and more complex quantum low-density parity-check codes efficiently suppress gate and shuttling noise to a level that allows for the execution of quantum algorithms within the classically intractable regime. This work thus brings us one step closer to the execution of quantum algorithms that outperform classical machines. Published by the American Physical Society 2024
Spin qubits in silicon quantum dot arrays are a promising quantum computation platform for long-term scalability due to their small qubit footprint and compatibility with advanced semiconductor manufacturing. However, spin qubit devices face a key architectural bottleneck: the large physical footprint of readout components relative to qubits prevents a dense layout where all qubits can be measured simultaneously, complicating the implementation of quantum error correction. This challenge is offset by the platform's unique rapid shuttling capability, which can be used to transport qubits to distant readout ports. In this work, we explore the design constraints and capabilities of spin qubits in silicon and propose the SNAQ (Shuttling-capable Narrow Array of spin Qubits) surface code architecture, which relaxes the 1:1 readout-to-qubit assumption by leveraging spin shuttling to time-multiplex ancilla qubit initialization and readout. Our analysis shows that, given sufficiently high (experimentally demonstrated) qubit coherence times, SNAQ delivers an orders-of-magnitude reduction in chip area per logical qubit. Additionally, by using a denser grid of physical qubits, SNAQ enables fast transversal logic for short-distance logical operations, achieving over 10x improvement in local logical clock speed while still supporting global operations via lattice surgery. This translates to a 3.2-5.7x improvement in key Adder and Lookup fault-tolerant subroutines. Our work pinpoints critical hardware metrics and provides a compelling path toward high-performance fault-tolerant computation on near-term-manufacturable spin qubit arrays.
Qubit shuttling promises to advance some quantum computing platforms to the qubit register sizes needed for effective quantum error correction (QEC), but also introduces additional errors whose impact must be evaluated. The established method to investigate the performance of QEC codes in a realistic scenario is to employ a standard noise model known as circuit-level noise, where all quantum operations are modeled as noisy. In the present work, we take this noise model and single out the effect of shuttling errors by introducing them as an additional so-called error location. This hardware abstraction is motivated by the SpinBus architecture and allows a systematic numerical investigation to map out the resulting two-dimensional parameter space. To this end, we take the Surface code and perform large scale simulations, most notably extracting the threshold across said two-dimensional parameter space. We study two scenarios for shuttling errors, depolarization on the one hand and dephasing on the other hand. For a purely dephasing shuttling error, we find a threshold of several percent, provided that all other operations have a high fidelity. The qubit overhead needed to reach a logical error rate of 10 − 12 (known as the "teraquop" regime \cite{Gidney2021Jul} increases only moderately for shuttling error rates up to about 1 % per shuttling operation. The error rates at which practically useful, i.e. well below threshold error correction is predicted to be possible are comfortably higher than what is expected to be achievable for spin qubits. Our results thus show that it is reasonable to expect shuttling operations to fall below threshold already at surprisingly large error rates. With realistic efforts in the near term, this offers positive prospects for spin qubit based quantum processors as a viable avenue for scalable fault-tolerant error-corrected quantum computing.
We present a fault-tolerant universal quantum computing architecture based on a code concatenation of biased-noise qubits and the parity architecture. The parity architecture can be understood as a low-density parity-check code tailored specifically to obtain any desired logical connectivity from nearest-neighbor physical interactions. The code layout can be dynamically adjusted to algorithmic requirements on the fly. This allows for implementations with any desired code distance with a universal set of fault-tolerant gates. In addition to the previously explored toolsets for concatenated cat codes, our approach features parallelizable interactions between arbitrary sets of qubits by directly addressing the parity qubits in the code. The proposed scheme supports codes with lower physical qubit overhead than the repetition code at the same code distances, while requiring only weight-3 and weight-4 stabilizers and nearest-neighbor connectivity on a two-dimensional square lattice.
This thesis presents multiple advances in the construction of noise-resistant quantum computers. In order to bridge the gap between abstract theory and practical experiments, my research encompasses a wide range of subfields within quantum computing, including error correction, silicon spin qubit physics and error mitigation. Firstly, I demonstrate that large-scale defects affecting entire regions of an error correcting code, such as cosmic rays or manufacturing defects, do not necessarily constitute a fundamental obstacle. Conversely, bespoke protocols that employ code deformation can be utilised to mitigate their impact, at a moderate resource overhead. Secondly, I investigate the feasibility of building a fault-tolerant silicon spin qubit quantum computer in the near term. I demonstrate that arranging the qubits in a 2×N array represents an effective methodology for the construction of error correcting codes, provided that the qubits can be shuttled with high fidelity. This expected characteristic of silicon spins can thus be utilised to circumvent the construction of complex dense 2D grids of qubits. Subsequently, I build upon the existing literature on the implementation of low-noise gates in silicon spin qubits, at the physical level this time. Specifically, I design a protocol for the individual control of silicon spin qubits, without the need for local magnetic fields targeting every qubit in the device. This simplification enables efficient control of silicon spins, whose single-qubit addressability was an identified bottleneck. Finally, I complement the above research with an error mitigation scheme targeted at the evaluation of eigenvalues with an early-fault-tolerant quantum computers. This scheme promises to alleviate the stringent resource costs of error correction, thereby paving the way for fault-tolerance in a nearer future.
Quantum computing has enormous potential, but this can only be realised if quantum errors can be controlled sufficiently to allow quantum algorithms to be completed reliably. However, quantum-error-corrected logical quantum bits (qubits) which can be said to have achieved meaningful error suppression have not yet been demonstrated. This thesis reports research on several topics related to the challenge of designing fault-tolerant quantum computers. The first topic is a proposal for achieving large-scale error correction with the surface code in a silicon donor based quantum computing architecture. This proposal relaxes some of the stringent requirements in donor placement precision set by previous ideas from the single atom level to the order of 10 nm in some regimes. This is shown by means of numerical simulation of the surface code threshold. The second topic then follows, it is the development of a method for benchmarking and assessing the performance of small error correcting codes in few-qubit systems, introducing a metric called 'integrity' - closely linked to the trace distance -- and a proposal for experiments to demonstrate various stepping stones on the way to 'strictly superior' quantum error correction. Most quantum error correcting codes, including the surface code, do not allow for fault-tolerant universal computation without the addition of extra gadgets. One method of achieving universality is through a process of distilling and then consuming high quality 'magic states'. This process adds additional overhead to quantum computation over and above that incurred by the use of the base level quantum error correction. The latter parts of this thesis report an investigation into how many physical qubits are needed in a `magic state factory' within a surface code quantum computer and introduce a number of techniques to reduce the overhead of leading magic state techniques. It is found that universal quantum computing is achievable with ∼ 16 million qubits if error rates across a device are kept below 10-4. In addition, the thesis introduces improved methods of achieving magic state distillation for unconventional magic states that allow for logical small angle rotations, and show that this can be more efficient than synthesising these operations from the gates provided by traditional magic states.
Quantum computers are far more error-prone than their classical counterparts. Therefore, to build a quantum computer capable of running large-scale quantum algorithms, we must use the techniques of quantum error correction to ensure that the computer produces the correct output even when its components are unreliable. However, the resource requirements of building such a fault-tolerant quantum computer are currently prohibitive. Here, we examine the utility of using three-dimensional (3D) surface codes in a fault-tolerant quantum computer. This family of topological error-correcting codes is a generalization of the well-known 2D surface code to three spatial dimensions. We show that certain 3D surface codes have a transversal logical non-Clifford gate. In a quantum computing architecture, a non-Clifford gate is required to achieve computational universality. Transversal gates do not entangle qubits in different codes, so they are naturally fault tolerant because they do not spread errors. Next, we consider the problem of decoding 3D surface codes. In a quantum error-correcting code, we cannot observe the qubits directly, so we measure parity-check operators to gain information about the state of the code. Decoding is the problem of estimating what error has occurred given a list of unsatisfied parity checks. We observe that 3D surface codes offer asymmetric protection against bit-flip and phase-flip errors, but in both cases, we find that a threshold error rate exists below which we can suppress logical errors by increasing the size of the code. We use our results about logical gates and decoding to propose two fault-tolerant quantum computing architectures that utilize 3D surface codes. Finally, we compare the resource requirements of our architectures with the requirements of leading quantum computing architectures based on topological codes. We find that one of our architectures may be competitive with the leading architectures, depending on the properties of the physical systems used to build the qubits.