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arXiv:2503.10601 · Quantum

Performance of the spin qubit shuttling architecture for a surface code implementation

Berat Yenilen, A. Sala, Hendrik Bluhm, Markus Müller, Manuel Rispler

Published Sep 30, 2026• 0 citations
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Abstract

Qubit shuttling promises to advance some quantum computing platforms to the qubit register sizes needed for effective quantum error correction (QEC), but also introduces additional errors whose impact must be evaluated. The established method to investigate the performance of QEC codes in a realistic scenario is to employ a standard noise model known as circuit-level noise, where all quantum operations are modeled as noisy. In the present work, we take this noise model and single out the effect of shuttling errors by introducing them as an additional so-called error location. This hardware abstraction is motivated by the SpinBus architecture and allows a systematic numerical investigation to map out the resulting two-dimensional parameter space. To this end, we take the Surface code and perform large scale simulations, most notably extracting the threshold across said two-dimensional parameter space. We study two scenarios for shuttling errors, depolarization on the one hand and dephasing on the other hand. For a purely dephasing shuttling error, we find a threshold of several percent, provided that all other operations have a high fidelity. The qubit overhead needed to reach a logical error rate of 10 − 12 (known as the "teraquop" regime \cite{Gidney2021Jul} increases only moderately for shuttling error rates up to about 1 % per shuttling operation. The error rates at which practically useful, i.e. well below threshold error correction is predicted to be possible are comfortably higher than what is expected to be achievable for spin qubits. Our results thus show that it is reasonable to expect shuttling operations to fall below threshold already at surprisingly large error rates. With realistic efforts in the near term, this offers positive prospects for spin qubit based quantum processors as a viable avenue for scalable fault-tolerant error-corrected quantum computing.

DOI
10.22331/q-2026-09-30-2219

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Qubit shuttling promises to advance some quantum computing platforms to the qubit register sizes needed for effective quantum error correction (QEC), but also introduces additional errors whose impact must be evaluated. The established method to investigate the performance of QEC codes in a realistic scenario is to employ a standard noise model known as circuit-level noise, where all quantum operations are modeled as noisy. In the present work, we take this noise model and single out the effect of shuttling errors by introducing them as an additional so-called error location. This hardware abstraction is motivated by the SpinBus architecture and allows a systematic numerical investigation to map out the resulting two-dimensional parameter space. To this end, we take the Surface code and perform large scale simulations, most notably extracting the threshold across said two-dimensional parameter space. We study two scenarios for shuttling errors, depolarization on the one hand and dephasing on the other hand. For a purely dephasing shuttling error, we find a threshold of several percent, provided that all other operations have a high fidelity. The qubit overhead needed to reach a logical error rate of 10 − 12 (known as the "teraquop" regime \cite{Gidney2021Jul} increases only moderately for shuttling error rates up to about 1 % per shuttling operation. The error rates at which practically useful, i.e. well below threshold error correction is predicted to be possible are comfortably higher than what is expected to be achievable for spin qubits. Our results thus show that it is reasonable to expect shuttling operations to fall below threshold already at surprisingly large error rates. With realistic efforts in the near term, this offers positive prospects for spin qubit based quantum processors as a viable avenue for scalable fault-tolerant error-corrected quantum computing.
We present a fault-tolerant mapping of rotated surface codes onto a 2×N2\times N2×N silicon spin-qubit railway architecture, utilizing electron shuttling to resolve the wiring fan-out bottleneck. Employing circuit-level noise modeling, we evaluate threshold performances across various noise biases. We demonstrate that shuttling check qubits instead of data qubits fundamentally improves system thresholds. Crucially, under a noise model biased towards dephasing for spin-qubit shuttling, the non-CSS XZZX surface code outperforms standard CSS variants. By tailoring the topological code to this specific inherent bias, we show that the Megaquop footprint is achievable with a distance 7 code requiring a p=10−3p = 10^{-3}p=10−3 physical error rate, highlighting a pathway for substantial hardware reductions in early fault-tolerant quantum processors.
As quantum computers scale toward millions of physical qubits, it becomes essential to robustly encode individual logical qubits to ensure fault tolerance under realistic noise. A high-quality foundational encoding allows future compilation techniques and heuristics to build on optimal or near-optimal layouts, improving scalability and error resilience. In this work, we synthesize a one-dimensional shuttling bus architecture for the rotated surface code, leveraging coherent spin-qubit shuttling, following a novel methodology we name Quantum Reverse Mapping. We formulate a mixed-integer optimization model that yields optimal solutions with relatively low execution time for small code distances, and propose a scalable heuristic that matches optimal results while maintaining linear computational complexity. We evaluate the synthesized architecture using architectural metrics, such as shuttling distance and cycle time, and full quantum simulations under realistic noise models, showing that the proposed design can sustain logical error rates as low as 2×10−102\times 10^{-10}2×10−10 per round at code distance 21, showcasing its feasibility for scalable quantum error correction in spin-based quantum processors.
It is well understood that a two-dimensional grid of locally interacting qubits is a promising platform for achieving fault-tolerant quantum computing. However in the near future, it may prove less challenging to develop lower-dimensional structures. In this paper, we show that such constrained architectures can also support fault tolerance; specifically we explore a 2 × N array of qubits where the interactions between non-neighboring qubits are enabled by shuttling the logical information along the rows of the array. Despite the apparent constraints of this setup, we demonstrate that error correction is possible and identify the classes of codes that are naturally suited to this platform. Focusing on silicon spin qubits as a practical example of qubits believed to meet our requirements, we provide a protocol for achieving full universal quantum computation with the surface code, while also addressing the additional constraints that are specific to a silicon spin-qubit device. Through numerical simulations, we evaluate the performance of this architecture using a realistic noise model, demonstrating that both surface code and more complex quantum low-density parity-check codes efficiently suppress gate and shuttling noise to a level that allows for the execution of quantum algorithms within the classically intractable regime. This work thus brings us one step closer to the execution of quantum algorithms that outperform classical machines. Published by the American Physical Society 2024
With fault-tolerant quantum computing (FTQC) on the horizon, it is critical to understand sources of logical errors in plausible hardware implementations of quantum error-correcting codes. Detailed error modeling of computational instructions on particular FTQC architectures will enable the better prediction of error propagation in FT-encoded quantum circuits while revealing where greater attention is needed in hardware design. In this work, we consider logical error rates for the surface code implemented on a hypothetical grid-based trapped-ion quantum charge-coupled device architecture. Specifically, we construct logical channels for the idling surface code and examine its diamond error under a mixed coherent and stochastic circuit-level noise model inspired by trapped ions. We include the coherent dephasing noise that is known to accumulate during physical qubit idling and transport in these systems, determining idling and transport durations using the time-resolved output of an open-source trapped-ion surface code compiler. To estimate expectation values of logical Pauli observables following hardware circuits containing non-Clifford sources of noise, we utilize a Monte Carlo technique to sample from an underlying quasiprobability distribution of Clifford circuits that we independently simulate in a phase-sensitive fashion. We verify error suppression up to code distance d = 11 at coherent dephasing rates near and below those of current-generation trapped-ion quantum computers and find that logical error rates align with those of analogous fully stochastic simulations in this regime. Exploring higher dephasing rates at d = 3 − 5 , we find evidence for growing coherent rotations about all three logical Pauli axes, increased diagonal logical error process matrix elements relative to those of stochastic simulations, and a reduced dephasing rate threshold. Overall, our work paves a way toward realistic hardware emulation of small fault-tolerant quantum processes, e.g., members of an FTQC instruction set.
Semiconductor spin qubits are a promising platform for large-scale quantum computing, but have yet to take full advantage of the broad class of quantum low-density parity check (QLDPC) codes, which promise high encoding rates and efficient logic but require nonlocal connectivity between physical qubits. In this work, we investigate the implementation of QLDPC codes on a tileable, shuttling-based spin qubit architecture. By tailoring syndrome extraction circuits to the shuttling noise model, we significantly improve on previous surface code proposals and extend the feasible shuttling range of the architecture by 5-10x, enabling the implementation of more complex codes with long-range interactions. Taking inspiration from the field of robotics, we develop a coordinated shuttle scheduling algorithm that supports arbitrary codes and use it to benchmark the logical performance of a variety of promising code families. We find that the optimized schedules are up to 86% faster than hand-optimized schedules for certain code families. Through detailed circuit-level simulations, we identify specific QLDPC codes that improve upon prior surface code implementations by orders of magnitude, increasing encoding efficiency and reducing logical error rates. This work demonstrates the potential of shuttling-based spin qubit hardware platforms for scalable and efficient fault-tolerant quantum computation.
Fast and high fidelity shuttling of spin qubits has been demonstrated in semiconductor quantum dot devices. Several architectures based on shuttling have been proposed; it has been suggested that singlet-triplet (dual-spin) qubits could be optimal for the highest shuttling fidelities. Here we present a fault-tolerant framework for quantum error correction based on such dual-spin qubits, establishing them as a natural realisation of erasure qubits within semiconductor architectures. We introduce a hardware-efficient leakage-detection protocol that automatically projects leaked qubits back onto the computational subspace, without the need for measurement feedback or increased classical control overheads. When combined with the XZZX surface code and leakage-aware decoding, we demonstrate a twofold increase in the error correction threshold and achieve orders-of-magnitude reductions in logical error rates. This establishes the singlet-triplet encoding as a practical route toward high-fidelity shuttling and erasure-based, fault-tolerant quantum computation in semiconductor devices.