This thesis presents multiple advances in the construction of noise-resistant quantum computers. In order to bridge the gap between abstract theory and practical experiments, my research encompasses a wide range of subfields within quantum computing, including error correction, silicon spin qubit physics and error mitigation. Firstly, I demonstrate that large-scale defects affecting entire regions of an error correcting code, such as cosmic rays or manufacturing defects, do not necessarily constitute a fundamental obstacle. Conversely, bespoke protocols that employ code deformation can be utilised to mitigate their impact, at a moderate resource overhead. Secondly, I investigate the feasibility of building a fault-tolerant silicon spin qubit quantum computer in the near term. I demonstrate that arranging the qubits in a 2×N array represents an effective methodology for the construction of error correcting codes, provided that the qubits can be shuttled with high fidelity. This expected characteristic of silicon spins can thus be utilised to circumvent the construction of complex dense 2D grids of qubits. Subsequently, I build upon the existing literature on the implementation of low-noise gates in silicon spin qubits, at the physical level this time. Specifically, I design a protocol for the individual control of silicon spin qubits, without the need for local magnetic fields targeting every qubit in the device. This simplification enables efficient control of silicon spins, whose single-qubit addressability was an identified bottleneck. Finally, I complement the above research with an error mitigation scheme targeted at the evaluation of eigenvalues with an early-fault-tolerant quantum computers. This scheme promises to alleviate the stringent resource costs of error correction, thereby paving the way for fault-tolerance in a nearer future.
This thesis presents multiple advances in the construction of noise-resistant quantum computers. In order to bridge the gap between abstract theory and practical experiments, my research encompasses a wide range of subfields within quantum computing, including error correction, silicon spin qubit physics and error mitigation. Firstly, I demonstrate that large-scale defects affecting entire regions of an error correcting code, such as cosmic rays or manufacturing defects, do not necessarily constitute a fundamental obstacle. Conversely, bespoke protocols that employ code deformation can be utilised to mitigate their impact, at a moderate resource overhead. Secondly, I investigate the feasibility of building a fault-tolerant silicon spin qubit quantum computer in the near term. I demonstrate that arranging the qubits in a 2×N array represents an effective methodology for the construction of error correcting codes, provided that the qubits can be shuttled with high fidelity. This expected characteristic of silicon spins can thus be utilised to circumvent the construction of complex dense 2D grids of qubits. Subsequently, I build upon the existing literature on the implementation of low-noise gates in silicon spin qubits, at the physical level this time. Specifically, I design a protocol for the individual control of silicon spin qubits, without the need for local magnetic fields targeting every qubit in the device. This simplification enables efficient control of silicon spins, whose single-qubit addressability was an identified bottleneck. Finally, I complement the above research with an error mitigation scheme targeted at the evaluation of eigenvalues with an early-fault-tolerant quantum computers. This scheme promises to alleviate the stringent resource costs of error correction, thereby paving the way for fault-tolerance in a nearer future.
The transition from noisy intermediate-scale quantum (NISQ) processors to large-scale fault-tolerant machines requires more than incremental improvements in physical qubit fidelity. While advances in quantum error correction (QEC) theory continue to lower the theoretical overhead of quantum computing, much of this research remains abstracted from the physical realities of qubit implementations. This disconnect often results in hardware-agnostic designs that are inefficient or impractical to build. In this dissertation, I identify three primary gaps between theoretical QEC research and practical hardware: (1) the high levels of noise and temporal instability in experimental devices that impede scalable QEC; (2) the prohibitively large qubit and time costs of useful algorithms, driven largely by the limitations of the standard surface code; and (3) the failure of current resource estimates to account for hardware-level constraints, such as limited connectivity and the complexity of implementing non-local operations. To bridge these gaps, I propose a holistic, cross-stack approach where the error correction protocols and the physical hardware are designed in concert. By developing realistic device models and hardware-aware solutions at the lowest levels of the software stack, we can accelerate the path toward functional fault-tolerance. I present my work across three research thrusts: first, leveraging codesign to mitigate hardware-specific noise and reduce physical error rates; second, developing software tools for fault-tolerant quantum computers to reduce the space-time overhead of the QEC layer; and third, proposing two novel hardware-aware QEC architectures that provide practical, high-performance routes to scalable quantum computation.
Quantum computation holds the promise of solving certain complex problems exponentially faster than classical computers. However, the high prevalent noise in current quantum devices impedes the accurate execution of even basic algorithms. This can be remedied by protecting quantum information with a quantum error-correcting code, where the logical information of an algorithmic qubit is spread across multiple physical qubits. Individual quantum errors are then located and corrected by the fault-tolerant measurement of multi-qubit stabilizer operators (parity checks). Unfortunately, error correction and fault tolerance both impose large demands on the qubit overhead: hundreds to thousands of physical qubits per logical qubit.
We reduce the spacetime cost of fault tolerance by redesigning key building blocks of an error-corrected quantum computer. First, we develop a combinatorial proof with flag fault tolerance that exponentially reduces the extra qubits needed to measure a stabilizer of any size, while tolerating one fault. We leverage these proofs to then design state preparation circuits for the Steane and Golay codes with 100% yield. Next, we improve error correction on a planar layout by showing that a distance-four code encoding six logical qubits protects information as well as the distance-five surface code, using one-tenth as many physical qubits. Finally, we optimize the time overhead of logical gates in surface code quantum computers by protecting measurement results with a classical code, cutting computation time by a factor of two to six. Our hardware-agnostic optimizations of fault tolerance overheads thus suggest new routes to advance the timeline of error-free quantum computing.
Quantum computers promise to solve computational problems that are inaccessible to classical machines. The reliable execution of large-scale quantum algorithms requires robust operations in the presence of noise. Quantum error correction addresses this challenge by encoding quantum information redundantly across several physical qubits, such that errors can be detected and corrected during a computation. However, no single error-correcting code intrinsically supports an inherently robust, fault-tolerant implementation of all gates needed for universal quantum computing. Moreover, most modern approaches to both quantum error correction and the implementation of universal logical operations on encoded qubits rely on mid-circuit measurements and feed-forward control. These types of operations are technologically demanding, often slow, and prone to high error rates, and they limit the overall success probability of quantum algorithms. In this thesis, we develop fault-tolerant protocols and circuits for quantum error correction and universal logical computation, with an emphasis on implementations compatible with current hardware systems. We first focus on fault-tolerant quantum error correction on small codes. By comparing different protocols, we identify trade-offs between compact circuit constructions and their robustness to noise. We then assess their practical performance by comparing numerical simulations of noisy circuits with experimental data. Beyond the preservation of encoded information, we study how universal logic can be implemented in a fault-tolerant manner on encoded qubits. A central approach considered in this thesis is code switching, in which logical information is transferred between two distinct error-correcting codes that support complementary sets of inherently fault-tolerant logical gates. In combination, these codes give access to a complete universal fault-tolerant logical gate set. In this thesis, we determine conditions that allow us to construct fault-tolerant protocols for code switching. We adapt these protocols to the capabilities of current hardware, thereby enabling the first experimental realization of universal fault-tolerant logic by means of code switching. However, the overall performance of these schemes is limited by slow and noisy mid-circuit measurements. To address this bottleneck, we construct a suite of measurement-free fault-tolerant universal operations that do not require any measurements during the execution of an algorithm. In this framework, error correction and logical operations are implemented coherently as part of the quantum circuit, without mid-circuit measurements or in-sequence classical control. We introduce measurement-free code-switching schemes that can be scaled to arbitrary code distances through concatenation, and which thereby provide, in principle, arbitrarily strong error suppression. We further tailor our approach to the capabilities of current trapped-ion quantum processors. New circuit constructions support the first experimental implementation of a logical quantum algorithm without mid-circuit measurements, demonstrated through Grover's search on three encoded qubits. Together, the results of this thesis expand the toolbox for early fault-tolerant quantum computation. They show how protocols for quantum error correction and universal logical gates can be designed without mid-circuit measurements with realistic hardware constraints in mind, opening new pathways towards universal quantum logic.
Quantum computation promises to revolutionize information processing by exploiting superposition and entanglement, enabling applications such as quantum simulation, combinatorial optimization, and secure quantum communication. Beyond individual processors, the quantum internet aims to connect quantum nodes through entanglement distribution, enabling distributed computation. However, quantum states are fragile: environmental interactions, imperfect gate operations, and measurement errors can quickly degrade encoded information. Reliable quantum computation therefore requires carefully designed quantum error-correcting codes and fault-tolerant protocols. Unlike classical redundancy schemes, quantum error correction must preserve delicate phase relationships and relies on indirect error detection through syndrome extraction with ancillary qubits, enabling error identification without collapsing encoded states. Topological codes, in particular, emerged early as the preferred choice for many architectures due to their planar structure, local interactions, and natural support for fault-tolerant logical operations. Color codes, for instance, allow transversal implementation of all Clifford gates, whereas non-Clifford operations require magic-state injection. More recent constructions, including quantum low-density parity-check codes, offer higher encoding rates and reduced resource overhead, but require long-range qubit connectivity and more complex protocols. Despite experimental progress, several challenges remain. Many platforms exhibit biased noise, motivating codes that exploit channel asymmetry. Real-time decoding remains a critical bottleneck, as fault-tolerant computation requires low-latency processing of rapidly generated syndrome data. Fault-tolerant logical state initialization also remains resource-intensive and scales poorly with code distance. Addressing these challenges, this thesis develops a unified framework spanning theory and experiment. It provides precise performance analysis of quantum error-correcting codes in the low physical error-rate regime, introduces codes tailored to biased noise, develops fast low-complexity decoding algorithms for real-time operation, and presents modular and efficient protocols for fault-tolerant state preparation of CSS codes. The latter is demonstrated experimentally through the preparation of a logical zero state of the Golay code on the Quantinuum H2 trapped-ion quantum computer.
A major obstacle towards realizing a practical quantum computer is the noise that arises due to system-environment interactions. While it is very well known that quantum error correction (QEC) provides a way to protect against errors that arise due to the noise affecting the system, a perfect quantum code requires atleast five physical qubits to observe a noticeable improvement over the no-QEC scenario. However, in cases where the noise structure in the system is already known, it might be more useful to consider quantum codes that are adapted to specific noise models. It is already known in the literature that such codes are resource efficient and perform on par with the standard codes. In this spirit, we address the following questions concerning such adaptive quantum codes in this thesis. (a) Construction: Given a noise model, we propose a simple and fast numerical optimization algorithm to search for good quantum codes. (b) Application: As a simple application of noise-adapted codes, we propose an adaptive QEC protocol that allows transmission of quantum information from one site to the other over a 1-d spin chain with high fidelity. (c) Fault-tolerance: Finally, we address the question of whether such noise-adapted QEC protocols can be made fault-tolerant starting with a [[4,1]] code and obtain a rigorous lower bound on threshold.
Quantum computing is entering a period in which progress will be shaped as much by advances in computer science as by improvements in hardware. The central thesis of this report is that early fault-tolerant quantum computing shifts many of the primary bottlenecks from device physics alone to computer-science-driven system design, integration, and evaluation. While large-scale, fully fault-tolerant quantum computers remain a long-term objective, near- and medium-term systems will support early fault-tolerant computation with small numbers of logical qubits and tight constraints on error rates, connectivity, latency, and classical control. How effectively such systems can be used will depend on advances across algorithms, error correction, software, and architecture. This report identifies key research challenges for computer scientists and organizes them around these four areas, each centered on a fundamental question.