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arXiv:2404.11332 · Physical Review Applied

Fault-tolerant quantum computing with the parity code and biased-noise qubits

Anette Messinger, Valentin Torggler, Berend Klaver, Michael Fellner, Wolfgang Lechner

Published Apr 14, 2025• 6 citations
arXivHTMLPDF

Abstract

We present a fault-tolerant universal quantum computing architecture based on a code concatenation of biased-noise qubits and the parity architecture. The parity architecture can be understood as a low-density parity-check code tailored specifically to obtain any desired logical connectivity from nearest-neighbor physical interactions. The code layout can be dynamically adjusted to algorithmic requirements on the fly. This allows for implementations with any desired code distance with a universal set of fault-tolerant gates. In addition to the previously explored toolsets for concatenated cat codes, our approach features parallelizable interactions between arbitrary sets of qubits by directly addressing the parity qubits in the code. The proposed scheme supports codes with lower physical qubit overhead than the repetition code at the same code distances, while requiring only weight-3 and weight-4 stabilizers and nearest-neighbor connectivity on a two-dimensional square lattice.

DOI
10.1103/physrevapplied.23.044032

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We present a fault-tolerant universal quantum computing architecture based on a code concatenation of biased-noise qubits and the parity architecture. The parity architecture can be understood as a low-density parity-check code tailored specifically to obtain any desired logical connectivity from nearest-neighbor physical interactions. The code layout can be dynamically adjusted to algorithmic requirements on the fly. This allows for implementations with any desired code distance with a universal set of fault-tolerant gates. In addition to the previously explored toolsets for concatenated cat codes, our approach features parallelizable interactions between arbitrary sets of qubits by directly addressing the parity qubits in the code. The proposed scheme supports codes with lower physical qubit overhead than the repetition code at the same code distances, while requiring only weight-3 and weight-4 stabilizers and nearest-neighbor connectivity on a two-dimensional square lattice.
We present a fault-tolerant quantum computing architecture based on a code concatenation of the parity code. In addition to the recently explored concatenation with bosonic (i.e. continuous-variable) qubits, we propose and study a concatenation with discrete-variable stabilizer codes. The parity code can be understood as a low-density-parity-check (LDPC) code tailored specifically to obtain any desired logical connectivity from nearest neighbor physical interactions. On the bosonic side, the proposed scheme enables codes with better encoding rate compared to the repetition code with the same code distances, while requiring only weight-3 and weight-4 stabilizers and nearest neighbor 2D square-lattice connectivity. On the discrete-variable side, the proposed scheme enables Calderbank-Shor-Steane (CSS) codes with less physical qubits overhead compared to the surface code but they do not form a quantum LDPC family.
It is well understood that a two-dimensional grid of locally interacting qubits is a promising platform for achieving fault-tolerant quantum computing. However in the near future, it may prove less challenging to develop lower-dimensional structures. In this paper, we show that such constrained architectures can also support fault tolerance; specifically we explore a 2 × N array of qubits where the interactions between non-neighboring qubits are enabled by shuttling the logical information along the rows of the array. Despite the apparent constraints of this setup, we demonstrate that error correction is possible and identify the classes of codes that are naturally suited to this platform. Focusing on silicon spin qubits as a practical example of qubits believed to meet our requirements, we provide a protocol for achieving full universal quantum computation with the surface code, while also addressing the additional constraints that are specific to a silicon spin-qubit device. Through numerical simulations, we evaluate the performance of this architecture using a realistic noise model, demonstrating that both surface code and more complex quantum low-density parity-check codes efficiently suppress gate and shuttling noise to a level that allows for the execution of quantum algorithms within the classically intractable regime. This work thus brings us one step closer to the execution of quantum algorithms that outperform classical machines. Published by the American Physical Society 2024
Vast numbers of qubits will be needed for large-scale quantum computing because of the overheads associated with error correction. We present a scheme for low-overhead fault-tolerant quantum computation based on quantum low-density parity-check (LDPC) codes, where long-range interactions enable many logical qubits to be encoded with a modest number of physical qubits. In our approach, logic gates operate via logical Pauli measurements that preserve both the protection of the LDPC codes and the low overheads in terms of the required number of additional qubits. Compared with surface codes with the same code distance, we estimate order-of-magnitude improvements in the overheads for processing around 100 logical qubits using this approach. Given the high thresholds demonstrated by LDPC codes, our estimates suggest that fault-tolerant quantum computation at this scale may be achievable with a few thousand physical qubits at comparable error rates to what is needed for current approaches.
We present a set of efficiently implementable logical multi-qubit gates in concatenated quantum error correction codes using parity qubits. In particular, we show how fault-tolerant high-weight rotation gates of arbitrary angle can be implemented on single physical qubits of a classical stabilizer code, or on localized regions of full quantum error correction codes. Similarly, we show how transversal CNOT gates can implement logical parity-controlled-NOT operations between arbitrarily many logical qubits. Both operation types can be implemented and in many cases parallelized without the use of lattice surgery or the need for complicated routing operations.
Abstract The main obstacle to large scale quantum computing are the errors present in every physical qubit realization. Correcting these errors requires a large number of additional qubits. Two main avenues to reduce this overhead are (i) low-density parity check (LDPC) codes requiring very few additional qubits to correct errors (ii) cat qubits where bit-flip errors are exponentially suppressed by design. In this work, we combine both approaches to obtain an extremely low overhead architecture. Assuming a physical phase-flip error probability ϵ ≈ 0.1% per qubit and operation, one hundred logical qubits can be implemented on a 758 cat qubit chip, with a total logical error probability per cycle and per logical qubit ϵ L ≤ 10 −8 . Our architecture also features two major advantages. First, the hardware implementation of the code can be realised with short-range qubit interactions in 2D and low-weight stabilizers, under constraints similar to those of the popular surface code architecture. Second, we demonstrate how to implement a fault-tolerant universal set of logical gates with an additional layer of routing cat qubits stacked on top of the LDPC layer, while maintaining the local connectivity. Furthermore, our architecture benefits from a high capacity of parallelization for these logical gates.
Fault-tolerant quantum computation allows quantum computations to be carried out while resisting unwanted noise. Several error-correcting codes have been developed to achieve this task, but none alone are capable of transversal universal quantum computation. This universality is highly desired and often achieved using techniques such as code concatenation, code switching, magic state distillation, or pieceable fault tolerance. Existing constructions can incur substantial overhead or rely on properties specific to particular codes. This work proposes implementing logical Clifford and T gates through novel, ancilla-mediated, pieceable interactions to construct a universal fault-tolerant quantum gate set. Our construction is deterministic, does not modify the underlying data codes or registers, and is generic over all data stabilizer codes. Thus, any single code becomes capable of universal quantum computation by leveraging helper codes in ancilla registers and mid-circuit measurements. Furthermore, since these logical gates are stabilizer code-generic, these implementations enable communication between heterogeneous stabilizer codes.