Abstract The main obstacle to large scale quantum computing are the errors present in every physical qubit realization. Correcting these errors requires a large number of additional qubits. Two main avenues to reduce this overhead are (i) low-density parity check (LDPC) codes requiring very few additional qubits to correct errors (ii) cat qubits where bit-flip errors are exponentially suppressed by design. In this work, we combine both approaches to obtain an extremely low overhead architecture. Assuming a physical phase-flip error probability ϵ ≈ 0.1% per qubit and operation, one hundred logical qubits can be implemented on a 758 cat qubit chip, with a total logical error probability per cycle and per logical qubit ϵ L ≤ 10 −8 . Our architecture also features two major advantages. First, the hardware implementation of the code can be realised with short-range qubit interactions in 2D and low-weight stabilizers, under constraints similar to those of the popular surface code architecture. Second, we demonstrate how to implement a fault-tolerant universal set of logical gates with an additional layer of routing cat qubits stacked on top of the LDPC layer, while maintaining the local connectivity. Furthermore, our architecture benefits from a high capacity of parallelization for these logical gates.
Abstract The main obstacle to large scale quantum computing are the errors present in every physical qubit realization. Correcting these errors requires a large number of additional qubits. Two main avenues to reduce this overhead are (i) low-density parity check (LDPC) codes requiring very few additional qubits to correct errors (ii) cat qubits where bit-flip errors are exponentially suppressed by design. In this work, we combine both approaches to obtain an extremely low overhead architecture. Assuming a physical phase-flip error probability ϵ ≈ 0.1% per qubit and operation, one hundred logical qubits can be implemented on a 758 cat qubit chip, with a total logical error probability per cycle and per logical qubit ϵ L ≤ 10 −8 . Our architecture also features two major advantages. First, the hardware implementation of the code can be realised with short-range qubit interactions in 2D and low-weight stabilizers, under constraints similar to those of the popular surface code architecture. Second, we demonstrate how to implement a fault-tolerant universal set of logical gates with an additional layer of routing cat qubits stacked on top of the LDPC layer, while maintaining the local connectivity. Furthermore, our architecture benefits from a high capacity of parallelization for these logical gates.
Vast numbers of qubits will be needed for large-scale quantum computing because of the overheads associated with error correction. We present a scheme for low-overhead fault-tolerant quantum computation based on quantum low-density parity-check (LDPC) codes, where long-range interactions enable many logical qubits to be encoded with a modest number of physical qubits. In our approach, logic gates operate via logical Pauli measurements that preserve both the protection of the LDPC codes and the low overheads in terms of the required number of additional qubits. Compared with surface codes with the same code distance, we estimate order-of-magnitude improvements in the overheads for processing around 100 logical qubits using this approach. Given the high thresholds demonstrated by LDPC codes, our estimates suggest that fault-tolerant quantum computation at this scale may be achievable with a few thousand physical qubits at comparable error rates to what is needed for current approaches.
It is widely accepted that quantum error correction is essential for realizing large-scale fault-tolerant quantum computing. Recent experiments have demonstrated error correction codes operating below threshold, primarily using local planar codes such as the surface code and color code. In parallel, theoretical advances in quantum low-density parity-check (LDPC) codes promise significantly lower overheads, albeit at the cost of requiring non-local parity checks. While these results are encouraging, implementing such codes remains challenging for near-term experiments, creating obstacles to holistic benchmarking of hardware architectures capable of supporting long-range couplers. In this work, we present a simple construction recipe for small quantum LDPC codes based on recent developments in the field. Our codes are approximately twice as efficient as comparable surface codes, yet require only weight-four parity checks, which simplifies experimental realization compared to other quantum LDPC codes. We provide concrete proposals for implementations with superconducting qubits in flip-chip architectures and with semiconductor spin qubits using shuttling-based approaches.
We propose a fault-tolerant quantum computer architecture for trapped-ion devices, which we call the walking cat architecture. Our blueprint includes a compiler, a detailed description of all the quantum error-correction protocols, a micro-architecture, a sufficiently fast decoder, and thorough simulations. The backbone of the architecture is a cat factory, producing cat states distributed throughout the machine, which are consumed to perform logical operations. The walking cat architecture is based entirely on a modern quantum error-correction approach called low-density parity-check (LDPC) codes.
We identify promising instances of the walking cat architecture, such as (1) a simple architecture based on a single LDPC code, (2) a fast architecture based on fast logical gates relying on a [[70, 6, 9]] code, equipped with Clifford-frame tracking for any 6-qubit Clifford gate, and (3) a dense architecture based on a [[102, 22, 9]]] code encoding 22 logical qubits per memory block. Our dense architecture provides a design with 110 logical qubits executing about one million T gates per day using only 2,514 physical qubits. We estimate that the quantum Hamiltonian simulation of a Heisenberg model on 100 sites can be executed within one month with 10,000 physical qubits, including all shots required to achieve chemical accuracy, suggesting that such a device could enter the regime of classically intractable physics simulations.
Our design relies on hardware components that have been experimentally demonstrated on small devices. We emphasize simplicity over hypothetical performance to facilitate the practical realization of this machine. Based on this approach, we believe that a fault-tolerant quantum computer with hundreds of logical qubits capable of running millions of logical gates can be built in the near term, providing a platform to explore a broad range of applications.
High-rate quantum error correcting (QEC) codes with moderate overheads in qubit number and control complexity are highly desirable for achieving fault-tolerant quantum computing. Recently, quantum error correction has experienced significant progress both in code development and experimental realizations, with neutral atom qubit architecture rapidly establishing itself as a leading platform in the field. Scalable quantum computing will require processing with QEC codes that have low qubit overhead and large error suppression, and while such codes do exist, they involve a degree of non-locality that has yet to be integrated into experimental platforms. In this work, we analyze a family of high-rate Low-Density Parity-Check (LDPC) codes with limited long-range interactions and outline a near-term implementation in neutral atom registers. By means of circuit-level simulations, we find that these codes outperform surface codes in all respects when the two-qubit nearest neighbour gate error probability is below ~ 0.1%. By using multiple laser colors, we show how these codes can be natively integrated in two-dimensional static neutral atom qubit architectures with open boundaries, where the desired long-range connectivity can be targeted via the Rydberg blockade interaction. Quantum error correction codes with low qubit overhead and error suppression capabilities are highly desirable for fault-tolerant quantum computing. Here, the authors introduce a family of high-rate Low Density Parity-Check quantum error correcting codes with moderate long-range connectivity and outline a near-term implementation in static neutral atom registers.
Quantum low-density parity-check (qLDPC) codes are promising candidates for realizing large-scale fault-tolerant quantum computing. Although many codes with favorable theoretical parameters have been developed, their practical adoption must take hardware implementability into account. For mainstream quantum platforms such as superconductors and neutral atoms, the connectivity, the length of non-local couplings, and the complexity of wiring or atom rearrangement are key factors that dictate the difficulty of hardware realization. Here, we propose a new family of qLDPC codes, termed routing codes. Within this family, we find explicit instances whose encoding rates are competitive to those of bivariate bicycle (BB) codes, while systematically reducing qubit connectivity, shortening the length of non-local couplings, and, crucially, making all non-local couplings mutually parallel. This parallelism translates into quantifiable benefits, substantially reducing wiring crossings in superconducting multi-layer architectures and simplifying the scheduling of atom movement in neutral-atom arrays. The weight-7 routing codes maintain a high threshold of 0.7\% and reduce the physical qubit overhead by approximately a factor of 8, compared to surface codes achieving a same logical error rate. Further increasing the weight to 11 yields a [[200, 24, 14]] and [[200, 16, 17]] codes with an encoding rate over 23 times that of the surface code, at the cost of a higher logical error rate. These results establish routing codes as a hardware-centric qLDPC family that bridges the gap between theoretical optimality and near-term physical feasibility.
Quantum low density parity check (LDPC) codes may provide a path to build low-overhead fault-tolerant quantum computers. However, as general LDPC codes lack geometric constraints, naïve layouts couple many distant qubits with crossing connections which could be hard to build in hardware and could result in performance-degrading crosstalk. We propose a 2D layout for quantum LDPC codes by decomposing their Tanner graphs into a small number of planar layers. Each layer contains long-range connections which do not cross. For any Calderbank-Shor-Steane code with a degree-δ Tanner graph, we design stabilizer measurement circuits with depth at most (2δ+2) using at most ⌈δ/2⌉ layers. We observe a circuit-noise threshold of 0.28% for a positive-rate code family using 49 physical qubits per logical qubit. For a physical error rate of 10^{-4}, this family reaches a logical error rate of 10^{-15} using fourteen times fewer physical qubits than the surface code.