The state of the art of quantum circuits using the ripple-carry strategy for the addition and comparison of two n-bit numbers is presented, as well as optimizations in the Clifford+ <?TeX $\mathsf {T}$?> Math 1 gate set, both in terms of <?TeX $\mathsf {CNOT}$?> Math 2 -depth and <?TeX $\mathsf {T}$?> Math 3 -depth, or <?TeX $\mathsf {CNOT}$?> Math 4 -count and <?TeX $\mathsf {T}$?> Math 5 -count. In particular, we consider the adders presented by Cuccaro et al. and Takahashi et al., and exhibit an adder with a <?TeX $\mathsf {T}$?> Math 6 -depth of 3n and a <?TeX $\mathsf {CNOT}$?> Math 7 -depth of 8n, while without optimization of the original circuits, a <?TeX $\mathsf {T}$?> Math 8 -depth of 6n is expected. Note that we have focused here on quantum ripple-carry adders using at most one ancilla, without any approximation of the 3-qubit gates involved (Toffoli, Peres and TR) or any strategy involving a measurement.
The state of the art of quantum circuits using the ripple-carry strategy for the addition and comparison of two n-bit numbers is presented, as well as optimizations in the Clifford+ <?TeX $\mathsf {T}$?> Math 1 gate set, both in terms of <?TeX $\mathsf {CNOT}$?> Math 2 -depth and <?TeX $\mathsf {T}$?> Math 3 -depth, or <?TeX $\mathsf {CNOT}$?> Math 4 -count and <?TeX $\mathsf {T}$?> Math 5 -count. In particular, we consider the adders presented by Cuccaro et al. and Takahashi et al., and exhibit an adder with a <?TeX $\mathsf {T}$?> Math 6 -depth of 3n and a <?TeX $\mathsf {CNOT}$?> Math 7 -depth of 8n, while without optimization of the original circuits, a <?TeX $\mathsf {T}$?> Math 8 -depth of 6n is expected. Note that we have focused here on quantum ripple-carry adders using at most one ancilla, without any approximation of the 3-qubit gates involved (Toffoli, Peres and TR) or any strategy involving a measurement.
Approximate quantum adders are gaining traction in NISQ-era computing for their potential to reduce quantum resource usage while preserving computational accuracy. In this work, we evaluate two 8-qubit hybrid approximate quantum adders that combine a 2-qubit approximate block, either a pass-through Copy Adder or a CNOT-based design, with a 6-qubit Cuccaro ripple-carry adder. Simulations are conducted using IBM's Qiskit framework under realistic noise models, including bit-flip, depolarizing, and thermal noise. Compared to the exact 8-bit Cuccaro adder, our designs reduce quantum cost and circuit depth by over 20 percent and achieve up to 79.3 percent higher output probability under noisy conditions. These results highlight the robustness and efficiency of approximate logic in noisy quantum environments and confirm its practicality for near-term quantum hardware.
This paper presents the design, optimization, and simulation of arithmetic circuits using reversible logic for quantum computing applications. The motivation behind this work is to achieve resource-efficient computation through reduced quantum cost, minimized garbage outputs, and lower ancilla requirements. The methodology involves implementing Half Adders, Full Adders, Multiplexers, and Ripple Carry Adders (RCAs) using Toffoli and Peres gates. The proposed 8-bit RCA achieves a quantum cost of 58 using 24 qubits, 8 garbage outputs, and 6 ancilla inputs—showing a significant improvement over conventional Toffoli-based designs that require higher quantum cost and resources. Simulations were conducted on IBM Qiskit and Google Colab using the Qiskit SDK to validate circuit correctness and scalability. The obtained results demonstrate superior resource efficiency and confirm the feasibility of reversible-logic-based quantum arithmetic as a foundation for scalable quantum arithmetic logic units (ALUs) and processors.
We present quantum circuits for comparison and increment operations that achieve an asymptotically optimal gate count of Θ(n) and depth of Θ(logn) over the Clifford+Toffoli gate set, while using a provably minimal number of qubits. We extend these results to classical-quantum comparators, yielding an improved classical-quantum adder with an optimal qubit count. Given the ubiquity of these operations as algorithmic building blocks, our constructions translate directly into reduced circuit complexity for many quantum algorithms. As a notable example, they can be used to improve a space-efficient circuit for Shor's factoring algorithm, reducing circuit depth from O(n3) to O(n2log2n) without increasing either the qubit count or the asymptotic gate complexity. Underpinning these results is a general theorem demonstrating how to trade ancilla qubits for control qubits with low overhead in both depth and gate count, providing a broadly applicable tool for quantum circuit design.
Quantum computing (Q-computing) is a revolutionary technology that applies quantum mechanics (QM) to implement calculations significantly quicker than traditional computers. Q-computing employs Q-bits (qubits) rather than classical bits, which can take on a superposition state, making it possible to represent both 0 and 1 at once. This distinctive property allows qubits to perform multiple calculations simultaneously, making Q computers exponentially more powerful as more qubits are added, compared to the linear scaling of classical computers. However, challenges such as qubit instability and error rates remain significant obstacles to fully realizing this potential. A vital aspect of this technology is the development of Q arithmetic circuits, which act as the foundational blocks for efficiently executing Q algorithms. Q half-adder and full-adder circuits are integral to performing fundamental arithmetic operations within Q computers. In contrast to classical adders, Q adders rely on Q gates such as Controlled NOT (CNOT) and Toffoli gates. These gates exploit Q phenomena like entanglement and superposition, allowing for more efficient computations. The Q half-adder consists of two qubits and adds two single bits, producing a carry and sum output. It utilizes the CNOT gate to compute the sum and the Toffoli gate (controlled-controlled-NOT [CCNOT]) to compute the carry. The Q full-adder builds on this, adding three qubits to produce a sum and a carry output, further increasing computational capacity. Through the entanglement of qubits, these circuits allow for more parallelism and speed compared to classical adders. Q carry-look-ahead adders (QCLAs) and Q ripple-carry adders (QRCAs) are used to perform more complex arithmetic operations based on these half-adder and full-adder structures. Q arithmetic circuits have broad applications, boosting secure key generation in cryptography, speeding up matrix operations for faster model training in machine learning, and enabling more precise, efficient image transformations in Q image processing, benefiting fields like medical imaging and computer vision.
Addition is a key arithmetic operation in computing, as the rest of arithmetic operations are somewhat based on it. Focusing on quantum computing, addition can be implemented in different ways, such as adapting the ripple-carry adder from classical computing, or using a QFT-based adder, which is more efficient than the former. However, a Toffoli-based adder is in fact an alternative way to optimize QFT-based adders by merging rotation gates into a string of controlled-NOT and Toffoli gates with different control qubits. In this paper, the basics of matrix analysis of quantum circuits are described, which in turn are used to perform a matrix analysis of Toffoli adder circuits.
The basic components of both quantum and quantum-inspired arithmetic systems are quantum adders. Traditional direct quantum adders like the Vedral and Cuccaro ripple-carry adders provide accurate computation but have higher circuit depth, longer propagation delay and complexity of hardware implementation based upon extensive usage of Toffoli gates. This article brings about a comparison analysis of the current quantum adder designs, and it suggests an Approximate Toffoli Adder in order to enhance performance and hardware efficiency. The suggested design is designed with the help of Verilog HDL and run with Xilinx Vivado 2025.2. As can be seen from experimental results, the Vedral and Cuccaro adders have a critical path delay of 7.999 ns and 7.979 ns, respectively, and the total on-chip power consumption of 2.945 W. Conversely, the Approximate Toffoli Adder proposed has a low critical path delay of 7.261 ns, lower power consumption of 2.442 W and less hardware consumption with 18 logic cells than the current designs with 20 logic cells. Analysis of errors ensures that there is a minimal difference in the accuracy of the output. It is proven that approximate arithmetic offers a successful trade-off between precision, speed, and power efficiency to use in quantum-inspired computing.