We present a (REAS) technique to manage errors in quantum computers. Our method reduces the accumulation of errors in any quantum circuit composed of single- or two-qubit gates expressed as e − i σ θ for Pauli operators σ and θ ∈ [ 0 , π ) , which forms a universal gate set. For coherent errors, which include gate overrotation and crosstalk, we demonstrate a reduction of the error scaling in an L -depth circuit from O ( L ) to O ( L ) . This asymptotic error suppression behavior can be proven in a regime where all gates, including those constituting the error-suppressing protocol itself, are noisy. Going beyond coherent errors, we derive the general form of decoherence noise that can be suppressed by REAS. Lastly, we experimentally demonstrate the effectiveness of our approach regarding realistic errors using 100-qubit circuits with up to 64 two-qubit gate layers on IBM Quantum processors.
We present a (REAS) technique to manage errors in quantum computers. Our method reduces the accumulation of errors in any quantum circuit composed of single- or two-qubit gates expressed as e − i σ θ for Pauli operators σ and θ ∈ [ 0 , π ) , which forms a universal gate set. For coherent errors, which include gate overrotation and crosstalk, we demonstrate a reduction of the error scaling in an L -depth circuit from O ( L ) to O ( L ) . This asymptotic error suppression behavior can be proven in a regime where all gates, including those constituting the error-suppressing protocol itself, are noisy. Going beyond coherent errors, we derive the general form of decoherence noise that can be suppressed by REAS. Lastly, we experimentally demonstrate the effectiveness of our approach regarding realistic errors using 100-qubit circuits with up to 64 two-qubit gate layers on IBM Quantum processors.
Coherent errors, and especially those that occur in correlation among a set of qubits, are detrimental for large-scale quantum computing. Correlations in noise can occur as a result of spatial and temporal configurations of instructions executing on the quantum processor. In this paper, we perform a detailed experimental characterization of many of these error sources, and theoretically connect them to the physics of superconducting qubits and gate operations. Equipped with this knowledge, we devise compiler strategies to suppress these errors using dynamical decoupling or error compensation into the rest of the circuit. Importantly, these strategies are successful when the context at each layer of computation is taken into account: how qubits are connected, what crosstalk terms exist on the device, and what gates or idle periods occur in that layer. Our context-aware compiler thus suppresses some dominant sources of error, making further error mitigation or error correction substantially less expensive. For example, our experiments show an increase of 18.5% in layer fidelity for a candidate 10 -qubit circuit layer compared to context-unaware suppression. Owing to the exponential nature of error mitigation, these improvements due to error suppression translate to several orders of magnitude reduction of sampling overhead for a circuit consisting of a moderate number of layers.
Crosstalk and several forms of coherent noise are invisible when a qubit or a gate is calibrated or benchmarked in isolation. These are unlocked during the execution of a full quantum circuit applying entangling gates to several qubits simultaneously. Unitary crosstalk noise, such as an unwanted Z-Z coupling, limits the state fidelity during the execution of cross-resonance controlled-not (cnot) gates in superconductor quantum computers. This work presents (1) a method of tracing coherent errors by exploiting their sensitivity to the arrangement of cnot gates in the circuit and (2) a correction scheme that modifies the original circuit by inserting carefully the chosen compensating gates (single- or two-qubit) to possibly undo coherent errors. On two vastly different types of IBMQ processors offering quantum volume 8 to 32, our experimental results show up to 25% reduction in the infidelity of [[7,1,3]] code $|+\ensuremath{\rangle}$ state (Clifford circuits) and five- to 15-qubit W states (non-Clifford circuits). Our experimental circuits aggressively deploy forced commutation of cnot gates to obtain low-noise state-preparation circuits. An encoded state initialized with fewer errors marks an important step towards successful demonstration of fault-tolerant quantum computers.
We introduce crosstalk-robust gate sets, which are obtained using a novel, scalable optimal control problem exploiting locality. Through the suppression of pairwise quantum crosstalk, the gate sets enable robustness that extends to multi-qubit circuits. The IBM Quantum Platform devices provide a testbed for our gate sets, where we study their efficacy via error suppression protocols and randomized parallel single-qubit circuits of up to eight qubits. Furthermore, we provide the first known assessment of the impact of complete optimal control gate sets on quantum algorithms. Using a Hamiltonian simulation of a four-qubit transverse field Ising model, we show that noise-informed gates enhance median algorithmic performance by a factor of four over baseline Gaussian gates using the same calibration procedures. Lastly, we provide numerical evidence that optimized gate sets enable larger qubit-qubit coupling strengths that can cut two-qubit gate times in half. This result confirms that hardware-software co-design using quantum optimal control can create new opportunities for quantum computing architectures.
Near-term quantum computers have been built as intermediate-scale quantum devices and are fragile against quantum noise effects, namely, NISQ devices. Traditional quantum-error-correcting codes are not implemented on such devices and to perform quantum computation in good accuracy with these machines we need to develop alternative approaches for mitigating quantum computational errors. In this work, we propose quantum error mitigation (QEM) scheme for quantum computational errors which occur due to couplings with environments during gate operations, i.e., decoherence. To establish our QEM scheme, first we estimate the quantum noise effects on single-qubit states and represent them as groups of quantum circuits, namely, quantum-noise-effect circuit groups. Then our QEM scheme is conducted by subtracting expectation values generated by the quantum-noise-effect circuit groups from those obtained by the quantum circuits for the quantum algorithms under consideration. As a result, the quantum noise effects are reduced, and we obtain approximately the ideal expectation values via the quantum-noise-effect circuit groups and the numbers of elementary quantum circuits composing them scale polynomial with respect to the products of the depths of quantum algorithms and the numbers of register bits. To numerically demonstrate the validity of our QEM scheme, we run noisy quantum simulations of qubits under amplitude damping effects for four types of quantum algorithms. Furthermore, we implement our QEM scheme on IBM Q Experience processors and examine its efficacy. Consequently, the validity of our scheme is verified via both the quantum simulations and the quantum computations on the real quantum devices. Our QEM scheme is solely composed of quantum-computational operations (quantum gates and measurements), and thus, it can be conducted by any type of quantum device. In addition, it can be applied to error mitigation for many other types of quantum noise effects as well as noisy quantum computing of long-depth quantum algorithms.
Quantum circuit ensembles that have the properties of unitary k-designs represent applications where there is no obvious bias toward any particular Pauli support, as is the case in simulating systems exhibiting ''quantum chaos,'' which range from quantum dynamics near black holes to gapless spin fluid analysis. However, noisy hardware makes quantum circuits prone to a myriad of error sources, of which depolarizing and coherent error can be particularly destructive. To combat depolarizing error, popular techniques typically involve circuit or gate folding, which can be time-intensive procedures due to increased circuit depth and shot overhead. Other tensor-network-based mitigation techniques suffer from intractability in high-entanglement regimes. In this work, we leverage the structure of unitary k-design Pauli support distributions by introducing a technique we name ''circuit balancing,'' along with gate benchmarking data, in order to estimate circuit-wide depolarization. We describe how to invert the diagnosed circuit depolarization even in the presence of coherent error, via Pauli twirling. We provide asymptotics to estimate the number of twirls needed to maintain a desired output fidelity. We test our method numerically in a variety of simulation settings and find that it can significantly reduce average random circuit infidelity. Further, we employ our methods to find significant infidelity reductions when running a random circuit ensemble on a contemporary superconducting quantum computer, IBM Fez. Overall, we show that the method effectively reduces gate-based error for unitary k-designs without incurring any two-qubit gate overhead.
Quantum computing is entering a transitional regime between noisy intermediate-scale quantum (NISQ) processing and early fault-tolerant quantum computation (FTQC), in which increasingly capable hardware is beginning to support repeated syndrome measurements, partial error correction, and logical-qubit operations, while residual physical and logical errors remain non-negligible. In this regime, error suppression, error mitigation, and quantum error correction are increasingly better viewed as complementary layers of a unified error-reduction strategy rather than as separate approaches, with each acting at a different stage of the quantum computation to improve simulation reliability. Thus, in this review, we provide a practical and forward-looking overview of the principal hardware error sources and the corresponding error suppression and mitigation methods for reducing their impact across the current NISQ-FTQC transition. We discuss hardware-aware circuit design, coherent-error suppression, readout mitigation, noise extrapolation, classical inference, and software-supported workflows, with particular emphasis on their implementation on actual quantum processors. We further examine how error mitigation techniques can be adapted to encoded and logical-qubit settings so that they can operate alongside quantum error correction to suppress residual logical errors and improve the accuracy of computation in the early fault-tolerant regime.