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arXiv:2606.03891

Efficient Quantum Error Mitigation for Unitary k-Designs

Ayush Pancholy, K. Birgitta Whaley

quant-phSubmitted Jun 2, 2026• Announced Jun 3, 2026• 0 citations
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Abstract

Quantum circuit ensembles that have the properties of unitary k-designs represent applications where there is no obvious bias toward any particular Pauli support, as is the case in simulating systems exhibiting ''quantum chaos,'' which range from quantum dynamics near black holes to gapless spin fluid analysis. However, noisy hardware makes quantum circuits prone to a myriad of error sources, of which depolarizing and coherent error can be particularly destructive. To combat depolarizing error, popular techniques typically involve circuit or gate folding, which can be time-intensive procedures due to increased circuit depth and shot overhead. Other tensor-network-based mitigation techniques suffer from intractability in high-entanglement regimes. In this work, we leverage the structure of unitary k-design Pauli support distributions by introducing a technique we name ''circuit balancing,'' along with gate benchmarking data, in order to estimate circuit-wide depolarization. We describe how to invert the diagnosed circuit depolarization even in the presence of coherent error, via Pauli twirling. We provide asymptotics to estimate the number of twirls needed to maintain a desired output fidelity. We test our method numerically in a variety of simulation settings and find that it can significantly reduce average random circuit infidelity. Further, we employ our methods to find significant infidelity reductions when running a random circuit ensemble on a contemporary superconducting quantum computer, IBM Fez. Overall, we show that the method effectively reduces gate-based error for unitary k-designs without incurring any two-qubit gate overhead.

Comments
16 pages, 7 figures

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Quantum circuit ensembles that have the properties of unitary k-designs represent applications where there is no obvious bias toward any particular Pauli support, as is the case in simulating systems exhibiting ''quantum chaos,'' which range from quantum dynamics near black holes to gapless spin fluid analysis. However, noisy hardware makes quantum circuits prone to a myriad of error sources, of which depolarizing and coherent error can be particularly destructive. To combat depolarizing error, popular techniques typically involve circuit or gate folding, which can be time-intensive procedures due to increased circuit depth and shot overhead. Other tensor-network-based mitigation techniques suffer from intractability in high-entanglement regimes. In this work, we leverage the structure of unitary k-design Pauli support distributions by introducing a technique we name ''circuit balancing,'' along with gate benchmarking data, in order to estimate circuit-wide depolarization. We describe how to invert the diagnosed circuit depolarization even in the presence of coherent error, via Pauli twirling. We provide asymptotics to estimate the number of twirls needed to maintain a desired output fidelity. We test our method numerically in a variety of simulation settings and find that it can significantly reduce average random circuit infidelity. Further, we employ our methods to find significant infidelity reductions when running a random circuit ensemble on a contemporary superconducting quantum computer, IBM Fez. Overall, we show that the method effectively reduces gate-based error for unitary k-designs without incurring any two-qubit gate overhead.
We present a simple, malleable and low-overhead approach for improving generic biased quantum error mitigation (QEM) methods, achieving up to 15% fidelity improvements over standard QEM on 100-qubit circuits with up to 2000 entangling gates. We do so by constructing verifiable benchmark circuits which mirror the application circuit's native-gate structure and thus noise profile. These circuits can be used to benchmark and mitigate the bias of the underlying error mitigation method, requiring only the application circuit and hardware native gate set. We present two methods for generating benchmark circuits; one is agnostic to the target hardware at the expense of a small overhead of single-qubit gates, while the other is specific to the IBM superconducting hardware and has no gate overhead. As a corollary, we introduce benchmarked-noise zero-noise extrapolation (bnZNE) as a simple adaptation of zero-noise extrapolation (ZNE), one of the most popular error mitigation methods. We consider as an example the bias-mitigated ZNE and bnZNE of Trotterized Hamiltonian simulations, observing that our approaches outperform standard ZNE using both small-scale classical simulations and 100-qubit utility-scale experiments on the IBM superconducting hardware. We consider the measurement of both single-site observables as well as two-site correlations along a one-dimensional qubit chain. We also provide a software package for implementing the error mitigation techniques used in this research.
Measurement error mitigation (MEM) is essential for realizing reliable quantum computation. Model-free measurement error mitigation (MF-MEM) is an important class of MEM methods that employs Pauli twirling—typically with a random twirling set—to convert measurement noise into a state-independent scaling factor, thereby enabling error mitigation through simple calibration. However, such methods face prohibitive sampling overhead, limiting their scalability. To address this, we introduce subsystem-balanced Pauli twirling (SB-PT), a twirling method designed for MF-MEM that enforces Pauli operator balance on measuring subsystems to selectively suppress dominant measurement noise. Theoretically, for a weight- τ Pauli observable, SB-PT removes all independent error components using only O ( 4 τ ) random circuits, substantially reducing the sampling overhead over conventional Pauli twirling. This efficiency gain is most significant for sparse observables. To extend such resource-efficient mitigation to arbitrary observables, we generalize and integrate a hardware-efficient measurement transformation framework that converts high-weight Pauli operators into low-weight effective ones via linear-depth circuits. The circuit noise introduced during this transformation is jointly mitigated with native measurement noise using a unified twirling protocol, ensuring robust performance. Extensive numerical simulations demonstrate a greater than 16-fold improvement in sampling efficiency over conventional random twirling, with consistent performance gains across varying system sizes and error regimes. This work provides a resource-frugal and experimentally viable path toward high-fidelity measurement in near-term quantum devices.
Abstract Quantum noise limits the reliability of noisy intermediate-scale quantum (NISQ) devices. Quantum error mitigation (QEM) provides a near-term path to improved accuracy, with randomized compiling (RC) serving as a key technique for transforming arbitrary gate noise into a stochastic Pauli form. However, its sampling complexity grows exponentially with circuit depth, hindering practical use. We introduce twirling scheduling (TS), which groups gate cycles into configurable units twirled collectively. By incorporating pseudo-twirling for non-Clifford gates, TS reduces the sampling-space dimension, mitigating this exponential scaling. Our theoretical analysis provides rigorous error bounds. Numerical simulations on Quantum Approximate Optimization Algorithm circuits up to 50 layers show that TS reduces estimation error by approximately 62% compared to conventional RC under a very small sampling budget and maintains superior performance when combined with established QEM protocols, including zero-noise extrapolation, Clifford data regression, and virtual distillation. TS thus offers a scalable, practical advance for error-mitigated quantum computation on NISQ hardware.
Using near-term quantum computers to achieve a quantum advantage requires efficient strategies to improve the performance of the noisy quantum devices presently available. We develop and experimentally validate two efficient error mitigation protocols named ``Noiseless Output Extrapolation" and ``Pauli Error Cancellation" that can drastically enhance the performance of quantum circuits composed of noisy cycles of gates. By combining popular mitigation strategies such as probabilistic error cancellation and noise amplification with efficient noise reconstruction methods, our protocols can mitigate a wide range of noise processes that do not satisfy the assumptions underlying existing mitigation protocols, including non-local and gate-dependent processes. We test our protocols on a four-qubit superconducting processor at the Advanced Quantum Testbed. We observe significant improvements in the performance of both structured and random circuits, with up to 86% improvement in variation distance over the unmitigated outputs. Our experiments demonstrate the effectiveness of our protocols, as well as their practicality for current hardware platforms.
Generating samples from the output distribution of a quantum circuit is a ubiquitous task used as a building block of many quantum algorithms. Here we show how to accomplish this task on a noisy quantum processor lacking full-blown error correction for a special class of quantum circuits dominated by Clifford gates. Our approach is based on coherent Pauli checks (CPCs) that detect errors in a Clifford circuit by verifying commutation rules between random Pauli-type check operators and the considered circuit. Our main contributions are as follows. First, we derive a simple formula for the probability that a Clifford circuit protected by CPCs contains a logical error. In the limit of a large number of checks, the logical error probability is shown to approach the value $\ensuremath{\approx}7\ensuremath{\epsilon}n/5$, where nnn is the number of qubits and $\ensuremath{\epsilon}$ is the depolarizing error rate. Our formula agrees nearly perfectly with the numerical simulation results. Second, we show that CPCs are well suited for quantum processors with a limited qubit connectivity. For example, the difference between all-to-all and linear qubit connectivity is only a $3\ifmmode\times\else\texttimes\fi{}$ increase in the number of cnot gates required to implement CPCs. Third, we describe simplified one-sided CPCs, which are well suited for mitigating measurement errors in the single-shot settings. Finally, we report an experimental demonstration of CPCs with up to 10 logical qubits and more than 100 logical cnot gates. Our experimental results show that CPCs provide a marked improvement in the logical error probability for the considered task of sampling the output distribution of quantum circuits.
Generating samples from the output distribution of a quantum circuit is a ubiquitous task used as a building block of many quantum algorithms. Here we show how to accomplish this task on a noisy quantum processor lacking full-blown error correction for a special class of quantum circuits dominated by Clifford gates. Our approach is based on Coherent Pauli Checks (CPCs) that detect errors in a Clifford circuit by verifying commutation rules between random Pauli-type check operators and the considered circuit. Our main contributions are as follows. First, we derive a simple formula for the probability that a Clifford circuit protected by CPCs contains a logical error. In the limit of a large number of checks, the logical error probability is shown to approach the value ≈7εn/5{\approx}7εn/5≈7εn/5, where nnn is the number of qubits and εεε is the depolarizing error rate. Our formula agrees nearly perfectly with the numerical simulation results. Second, we show that CPCs are well-suited for quantum processors with a limited qubit connectivity. For example, the difference between all-to-all and linear qubit connectivity is only a 3X increase in the number of CNOT gates required to implement CPCs. Third, we describe simplified one-sided CPCs which are well-suited for mitigating measurement errors in the single-shot settings. Finally, we report an experimental demonstration of CPCs with up to 10 logical qubits and more than 100 logical CNOT gates. Our experimental results show that CPCs provide a marked improvement in the logical error probability for the considered task of sampling the output distribution of quantum circuits.