Mitigation of frequency collisions in superconducting quantum processors
Amr Osman, Jorge Fernández-Pendás, Christopher Warren, Sandoko Kosen, Marco Scigliuzzo, Anton Frisk Kockum, Giovanna Tancredi, Anita Fadavi Roudsari, Jonas Bylander
The reproducibility of qubit parameters is a challenge for scaling up superconducting quantum processors. Signal cross talk imposes constraints on the frequency separation between neighboring qubits. The frequency uncertainty of transmon qubits arising from the fabrication process is attributed to deviations in the Josephson junction area, tunnel barrier thickness, and the qubit shunt capacitor. We decrease the sensitivity to these variations by fabricating larger Josephson junctions and reduce the wafer-level standard deviation in resistance down to 2%. We characterize 32 identical transmon qubits and demonstrate the reproducibility of the qubit frequencies with a 40 MHz standard deviation (i.e., 1%) with qubit quality factors exceeding 2 million. We perform two-level-system (TLS) spectroscopy and observe no significant increase in the number of TLSs causing qubit relaxation. We further show by simulation that for our parametric-gate architecture, and accounting only for errors caused by the uncertainty of the qubit frequency, we can scale up to 100 qubits with an average of only three collisions between quantum-gate transition frequencies, assuming $2%$ cross talk and $99.9%$ target gate fidelity.
The reproducibility of qubit parameters is a challenge for scaling up superconducting quantum processors. Signal cross talk imposes constraints on the frequency separation between neighboring qubits. The frequency uncertainty of transmon qubits arising from the fabrication process is attributed to deviations in the Josephson junction area, tunnel barrier thickness, and the qubit shunt capacitor. We decrease the sensitivity to these variations by fabricating larger Josephson junctions and reduce the wafer-level standard deviation in resistance down to 2%. We characterize 32 identical transmon qubits and demonstrate the reproducibility of the qubit frequencies with a 40 MHz standard deviation (i.e., 1%) with qubit quality factors exceeding 2 million. We perform two-level-system (TLS) spectroscopy and observe no significant increase in the number of TLSs causing qubit relaxation. We further show by simulation that for our parametric-gate architecture, and accounting only for errors caused by the uncertainty of the qubit frequency, we can scale up to 100 qubits with an average of only three collisions between quantum-gate transition frequencies, assuming 2 cross talk and 99.9 target gate fidelity.
The cross-resonance gate (cr gate) architecture that exploits fixed-frequency transmon qubits and fixed couplings is a leading candidate for quantum computing. Nonetheless, without the tunability of qubit parameters such as qubit frequencies and couplings, gate operations can be limited by the presence of quantum crosstalk arising from the always-on couplings. When increasing system sizes, this can become even more serious, considering frequency collisions caused by fabrication uncertainties. Here, we introduce a cr-gate-based transmon architecture with passive mitigation of both quantum crosstalk and frequency collisions. Assuming typical parameters, we show that ZZ crosstalk can be suppressed while maintaining XY couplings to support fast, high-fidelity cr gates. The architecture also allows one to go beyond the existing literature by extending the operating regions in which fast, high-fidelity cr gates are possible, thus alleviating the frequency-collision issue. To examine the practicality, we analyze the cr-gate performance in multiqubit lattices and provide an intuitive model for identifying and mitigating the dominant source of error. For the state-of-the-art precision in setting frequencies, we further investigate its impact on the gates. We find that ZZ crosstalk and frequency collisions can be largely mitigated for neighboring qubits, while interactions beyond near-neighbor qubits can introduce new frequency collisions. As the strength is typically at the submegahertz level, adding weak off-resonant drives to selectively shift qubits can mitigate the collisions. This work could be useful for suppressing quantum crosstalk and improving gate fidelities in large-scale quantum processors based on fixed-frequency qubits and fixed couplings.
Abstract Quantum bits, or qubits, are an example of coherent circuits envisioned for next-generation computers and detectors. A robust superconducting qubit with a coherent lifetime of O(100 µs) is the transmon: a Josephson junction functioning as a non-linear inductor shunted with a capacitor to form an anharmonic oscillator. In a complex device with many such transmons, precise control over each qubit frequency is often required, and thus variations of the junction area and tunnel barrier thickness must be sufficiently minimized to achieve optimal performance while avoiding spectral overlap between neighboring circuits. Simply transplanting our recipe optimized for single, stand-alone devices to wafer-scale (producing 64, 1x1 cm dies from a 150 mm wafer) initially resulted in global drifts in room-temperature tunneling resistance of ± 30%. Inferring a critical current I c variation from this resistance distribution, we present an optimized process developed from a systematic 38 wafer study that results in < 3.5% relative standard deviation (RSD) in critical current ( ≡ σ I c / I c ) for 3000 Josephson junctions (both single-junctions and asymmetric SQUIDs) across an area of 49 cm2. Looking within a 1x1 cm moving window across the substrate gives an estimate of the variation characteristic of a given qubit chip. Our best process, utilizing ultrasonically assisted development, uniform ashing, and dynamic oxidation has shown σ I c / I c = 1.8% within 1x1 cm, on average, with a few 1x1 cm areas having σ I c / I c < 1.0% (equivalent to σ f / f < 0.5%). Such stability would drastically improve the yield of multi-junction chips with strict critical current requirements.
We introduce a simplified fabrication technique for Josephson junctions and demonstrate superconducting Xmon qubits with T1 relaxation times averaging above 50 μs (Q>1.5×106). Current shadow-evaporation techniques for aluminum-based Josephson junctions require a separate lithography step to deposit a patch that makes a galvanic, superconducting connection between the junction electrodes and the circuit wiring layer. The patch connection eliminates parasitic junctions, which otherwise contribute significantly to dielectric loss. In our patch-integrated cross-type junction technique, we use one lithography step and one vacuum cycle to evaporate both the junction electrodes and the patch. This eliminates a key bottleneck in manufacturing superconducting qubits by reducing the fabrication time and cost. In a study of more than 3600 junctions, we show an average resistance variation of 3.7% on a wafer that contains forty 0.5×0.5-cm2 chips, with junction areas ranging between 0.01 and 0.16 μm2. The average on-chip spread in resistance is 2.7%, with 20 chips varying between 1.4% and 2%. For the junction sizes used for transmon qubits, we deduce a wafer-level transition-frequency variation of 1.7%–2.5%. We show that 60%–70% of this variation is attributed to junction-area fluctuations, while the rest is caused by tunnel-junction inhomogeneity. Such high frequency predictability is a requirement for scaling-up the number of qubits in a quantum computer.
Fixed-frequency transmon quantum computers (QCs) have advanced in coherence times, addressability, and gate fidelities. Unfortunately, these devices are restricted by the number of on-chip qubits, capping processing power and slowing progress toward fault-tolerance. Although emerging transmon devices feature over 100 qubits, building QCs large enough for meaningful demonstrations of quantum advantage requires overcoming many design challenges. For example, today’s transmon qubits suffer from significant variation due to limited precision in fabrication. As a result, barring significant improvements in current fabrication techniques, scaling QCs by building ever larger individual chips with more qubits is hampered by device variation. Severe device variation that degrades QC performance is referred to as a defect. Here, we focus on a specific defect known as a frequency collision. When transmon frequencies collide, their difference falls within a range that limits two-qubit gate fidelity. Frequency collisions occur with greater probability on larger QCs, causing collision-free yields to decline as the number of on-chip qubits increases. As a solution, we propose exploiting the higher yields associated with smaller QCs by integrating quantum chiplets within quantum multi-chip modules (MCMs). Yield, gate performance, and application-based analysis show the feasibility of QC scaling through modularity. Our results demonstrate that chiplet architectures, relative to monolithic designs, benefit from average yield improvements ranging from 9.6 – 92.6 × for ≲5 qubit machines. In addition, our simulations explore the design space of chiplet systems and discover configurations that demonstrate average two-qubit gate infidelity reductions that are at best 0.815 × their monolithic counterpart. Finally, we observe that carefully-selected modular systems achieve fidelity improvements on a range of benchmark circuits.
Abstract As superconducting quantum circuits scale to larger sizes, the problem of frequency crowding proves a formidable task. Here we present a solution for this problem in fixed-frequency qubit architectures. By systematically adjusting qubit frequencies post-fabrication, we show a nearly tenfold improvement in the precision of setting qubit frequencies. To assess scalability, we identify the types of “frequency collisions” that will impair a transmon qubit and cross-resonance gate architecture. Using statistical modeling, we compute the probability of evading all such conditions, as a function of qubit frequency precision. We find that, without post-fabrication tuning, the probability of finding a workable lattice quickly approaches 0. However, with the demonstrated precisions it is possible to find collision-free lattices with favorable yield. These techniques and models are currently employed in available quantum systems and will be indispensable as systems continue to scale to larger sizes.
The temporal stability and reproducibility of qubit parameters are critical for the long-term operation and maintenance of superconducting quantum processors. In this work, we present a comprehensive longitudinal characterization of 27 frequency-tunable transmon qubits spanning over one year across four thermal cycles. Our results establish a distinct hierarchy of stability for superconducting hardware. We find that the intrinsic device parameters determining the qubit frequency and the baseline energy relaxation times (T1) exhibit high robustness against thermal stress, characterized by frequency deviations typically confined within 0.5\% and non-degraded coherence baselines. In stark contrast, the environmental variables, specifically the background magnetic flux offsets and the microscopic landscape of two-level system (TLS) defects, undergo a significant stochastic reconfiguration after each cycle. By employing frequency-dependent relaxation spectroscopy and a quantitative metric, the T1 Spectral Topography Fidelity, we demonstrate that thermal cycling acts as a ``hard reset'' for the local defect environment. This process introduces a level of spectral randomization equivalent to thousands of hours of continuous low-temperature evolution. These findings confirm that while the fabrication quality is preserved, the specific noise realization is statistically distinct for each thermal cycle, necessitating automated recalibration strategies for large-scale quantum systems.