Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Log inSign up
Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Blog
Job Board
Q3AS

© 2026 Aqora Quantum S.A.S.

TermsPrivacyLegal Notice

arXiv:2210.10921 · IEEE/ACM International Symposium on Microarchitecture (MICRO)

Scaling Superconducting Quantum Computers with Chiplet Architectures

Kaitlin N. Smith, Gokul Subramanian Ravi, Jonathan M. Baker, Frederic T. Chong

Published Oct 1, 2022• 61 citations
arXivHTMLPDF

Abstract

Fixed-frequency transmon quantum computers (QCs) have advanced in coherence times, addressability, and gate fidelities. Unfortunately, these devices are restricted by the number of on-chip qubits, capping processing power and slowing progress toward fault-tolerance. Although emerging transmon devices feature over 100 qubits, building QCs large enough for meaningful demonstrations of quantum advantage requires overcoming many design challenges. For example, today’s transmon qubits suffer from significant variation due to limited precision in fabrication. As a result, barring significant improvements in current fabrication techniques, scaling QCs by building ever larger individual chips with more qubits is hampered by device variation. Severe device variation that degrades QC performance is referred to as a defect. Here, we focus on a specific defect known as a frequency collision. When transmon frequencies collide, their difference falls within a range that limits two-qubit gate fidelity. Frequency collisions occur with greater probability on larger QCs, causing collision-free yields to decline as the number of on-chip qubits increases. As a solution, we propose exploiting the higher yields associated with smaller QCs by integrating quantum chiplets within quantum multi-chip modules (MCMs). Yield, gate performance, and application-based analysis show the feasibility of QC scaling through modularity. Our results demonstrate that chiplet architectures, relative to monolithic designs, benefit from average yield improvements ranging from 9.6 – 92.6 × for ≲5 qubit machines. In addition, our simulations explore the design space of chiplet systems and discover configurations that demonstrate average two-qubit gate infidelity reductions that are at best 0.815 × their monolithic counterpart. Finally, we observe that carefully-selected modular systems achieve fidelity improvements on a range of benchmark circuits.

DOI
10.1109/micro56248.2022.00078

Related papers

Scalability and modularity for transmon-based quantum processors

Christian Dickel

This thesis mainly summarizes two experiments that relate to building a quantum computer out of superconducting transmon qubits. Transmon qubits have emerged as one of the foremost solid state qubits, realizing processors with more than ten qubits and demonstrating small scale quantum algorithms as well as quantum error correction schemes. Right now, there is a race between different academic and industry research groups to scale up transmon qubit processors. The first experiment was a demonstration of qubit control by selective broadcasting in order to reduce the scaling of expensive electronics with the number of qubits for individual single-qubit control. We demonstrated that we can bring two transmon qubits to the same frequency (combining fabrication accuracy and in-situ fine tuning) and use the same hardware to control both, routing the pulses with a nanosecond-timescale vector switch matrix. Despite the compromises required by this technique, we show a scalable path to single qubit control beyond the threshold required for quantum error correction. In benchmarking, we take into account gate leakage due to the fact that transmons are fundamentally multi-level systems. In the second experiment we establish entanglement between two transmon qubits on different chips. We use an entanglement by measurement scheme and demonstrate that we can overcome minor fabrication imperfections by shaping our measurement pulses. Ultimately, performance is mainly limited by photon loss between the chips and up to the amplification chain. This entanglement mediated by traveling photons could be used to make a distributed transmon processor where computations are spread across several chip modules. This modularity could enable connectivities that cannot be realized on chip and ease fabrication requirements, as modules could be individually fabricated and selected. Thus, both of these experiments fit into the larger effort to converge on the hardware, control equipment and architecture of a future large-scale transmon quantum computer. Other experiments I contributed to are summarized in the conclusion chapter to show the diverse physics that can be studied in cQED experiments.

•Jan 1, 2018•2 citations

Mitigation of frequency collisions in superconducting quantum processors

Amr Osman, Jorge Fernández-Pendás, Christopher Warren +6 more

The reproducibility of qubit parameters is a challenge for scaling up superconducting quantum processors. Signal cross talk imposes constraints on the frequency separation between neighboring qubits. The frequency uncertainty of transmon qubits arising from the fabrication process is attributed to deviations in the Josephson junction area, tunnel barrier thickness, and the qubit shunt capacitor. We decrease the sensitivity to these variations by fabricating larger Josephson junctions and reduce the wafer-level standard deviation in resistance down to 2%. We characterize 32 identical transmon qubits and demonstrate the reproducibility of the qubit frequencies with a 40 MHz standard deviation (i.e., 1%) with qubit quality factors exceeding 2 million. We perform two-level-system (TLS) spectroscopy and observe no significant increase in the number of TLSs causing qubit relaxation. We further show by simulation that for our parametric-gate architecture, and accounting only for errors caused by the uncertainty of the qubit frequency, we can scale up to 100 qubits with an average of only three collisions between quantum-gate transition frequencies, assuming $2%$ cross talk and $99.9%$ target gate fidelity.

arXiv:2303.04663•Physical Review Research•Oct 2, 2023•41 citations

Long-range tunable coupler for modular fluxonium quantum processors

Peng Zhao, Peng Xu, Zheng-Yuan Xue

The path toward practical superconducting quantum processors requires the integration of a large number of high-performance qubits. Modular architectures could offer a way to address the scaling limitations of monolithic designs by partitioning a large quantum processor into physically separated modules, or chiplets, linked through long-range interconnects. In this context, although fluxonium qubits have emerged as a compelling platform for quantum computing due to their long coherence times and high-fidelity gates, existing coupling schemes remain restricted to qubits in close proximity on a single chip. This limitation inherently precludes the long-range interconnects essential for modular integration. In this work, we propose a long-range tunable coupler designed to interconnect fluxonium qubits separated by more than one centimeter, thereby supporting the realization of modular fluxonium quantum processors. Under realistic assumptions, the proposed coupler has the potential to achieve inter-module two-qubit gate performance, specifically sub-100-ns gates with intrinsic errors below $10^{-4}$, comparable to that of intra-module (intra-chiplet) gates, while enabling modular integration with low quantum crosstalk, a key requirement for scalable systems. We further discuss the integration of this coupler into modular fluxonium lattices and explore its feasibility for achieving the higher connectivity and longer coupling range required for complex quantum error correction codes. This work could contribute to the development of large-scale fluxonium quantum processors by bridging their demonstrated potential with modular scalability.

quant-pharXiv:2604.12261•Apr 15, 2026•0 citations

New design of three-qubit system with three transmons and a single fixed-frequency resonator coupler

Jeongsoo Kang, Chanpyo Kim, Younghun Kim +1 more

The transmon, which has a short gate time and remarkable scalability, is the most commonly utilized superconducting qubit, based on the Cooper pair box as a qubit or coupler in superconducting quantum computers. Lattice and heavy-hexagon structures are well-known large-scale configurations for transmon-based quantum computers that classical computers cannot simulate. These structures share a common feature: a resonator coupler that connects two transmon qubits. Although significant progress has been made in implementing quantum error correction and quantum computing using quantum error mitigation, fault-tolerant quantum computing remains unachieved due to the inherent vulnerability of these structures. This raises the question of whether the transmon-resonator-transmon structure is the best option for constructing a transmon-based quantum computer. To address this, we demonstrate that the average fidelity of CNOT gates can exceed 0.98 in a structure where a resonator coupler mediates the coupling of three transmon qubits. This result suggests that our novel structure could be a key method for increasing the number of connections among qubits while preserving gate performance in a transmon-based quantum computer.

arXiv:2412.15629•Scientific Reports•Apr 9, 2025•5 citations

Lattice patch structure for fixed-frequency transmon quantum computer with high-fidelity CNOT gates

Chanpyo Kim, Jeongsoo Kang, Younghun Kwon

Superconducting transmon processors represent a leading platform for large-scale quantum computing due to their high gate fidelities and scalability. However, conventional qubit-coupler-qubit (QCQ) architectures face critical physical and structural bottlenecks, notably frequency crowding [spectator qubit collisions] during system scaling and inefficient mapping onto the standard surface code.To overcome these limitations, we propose a novel lattice-patch architecture that couples four fixed-frequency transmons to a single fixed-frequency coupler.This design enhances qubit connectivity and maps directly onto the surface-code lattice unit [plaquette], thereby minimizing the compilation overhead associated with logical qubit implementation. Furthermore, utilizing an entirely fixed-frequency design intrinsically eliminates susceptibility to external flux noise, ensuring robust operational stability.Multi-level numerical simulations demonstrate CNOT gate fidelities exceeding 0.98 across all six connectivity directions within the patch. Nevertheless, the complex interaction network of the four-qubit architecture induces unintended residual phase accumulation during cross-resonance driving. This parasitic effect necessitates precise calibration, achievable via virtual $R_z$ gates [software phase updates]. Ultimately, our results establish the lattice-patch architecture as an efficient, robust building block for future fault-tolerant quantum computers.

quant-pharXiv:2606.27017•Jun 26, 2026•0 citations

Chipmunq: A Fault-Tolerant Compiler for Chiplet Quantum Architectures

Peter Wegmann, Aleksandra Świerkowska, Emmanouil Giortamis +1 more

As quantum computing advances toward fault-tolerance through quantum error correction, modular chiplet architectures have emerged to provide the massive qubit counts required while overcoming fabrication limits of monolithic chips. However, this transition introduces a critical compilation gap: existing frameworks cannot handle the scale of fault-tolerant quantum circuits while managing the noisy, sparse interconnects of chiplet backends. We present Chipmunq, the first hardware-aware compiler for mapping and routing fault-tolerant circuits onto modular architectures. Chipmunq employs a quantum-error-correction-aware partitioning strategy that preserves the integrity of logical qubit patches, preventing prohibitive gate overheads common in general-purpose compilers. Our evaluation demonstrates that Chipmunq achieves a 13.5x speedup in compilation time compared to state-of-the-art tools. By incorporating chiplet constraints and defective qubits, it reduces circuit depth by 86.4% and SWAP gate counts by 91.4% across varying code distances. Crucially, Chipmunq overcomes heterogeneous inter-chiplet links, improving logical error rates by up to two orders of magnitude.

quant-pharXiv:2603.16389•Mar 18, 2026•0 citations
Fixed-frequency transmon quantum computers (QCs) have advanced in coherence times, addressability, and gate fidelities. Unfortunately, these devices are restricted by the number of on-chip qubits, capping processing power and slowing progress toward fault-tolerance. Although emerging transmon devices feature over 100 qubits, building QCs large enough for meaningful demonstrations of quantum advantage requires overcoming many design challenges. For example, today’s transmon qubits suffer from significant variation due to limited precision in fabrication. As a result, barring significant improvements in current fabrication techniques, scaling QCs by building ever larger individual chips with more qubits is hampered by device variation. Severe device variation that degrades QC performance is referred to as a defect. Here, we focus on a specific defect known as a frequency collision. When transmon frequencies collide, their difference falls within a range that limits two-qubit gate fidelity. Frequency collisions occur with greater probability on larger QCs, causing collision-free yields to decline as the number of on-chip qubits increases. As a solution, we propose exploiting the higher yields associated with smaller QCs by integrating quantum chiplets within quantum multi-chip modules (MCMs). Yield, gate performance, and application-based analysis show the feasibility of QC scaling through modularity. Our results demonstrate that chiplet architectures, relative to monolithic designs, benefit from average yield improvements ranging from 9.6 – 92.6 × for ≲5 qubit machines. In addition, our simulations explore the design space of chiplet systems and discover configurations that demonstrate average two-qubit gate infidelity reductions that are at best 0.815 × their monolithic counterpart. Finally, we observe that carefully-selected modular systems achieve fidelity improvements on a range of benchmark circuits.
This thesis mainly summarizes two experiments that relate to building a quantum computer out of superconducting transmon qubits. Transmon qubits have emerged as one of the foremost solid state qubits, realizing processors with more than ten qubits and demonstrating small scale quantum algorithms as well as quantum error correction schemes. Right now, there is a race between different academic and industry research groups to scale up transmon qubit processors. The first experiment was a demonstration of qubit control by selective broadcasting in order to reduce the scaling of expensive electronics with the number of qubits for individual single-qubit control. We demonstrated that we can bring two transmon qubits to the same frequency (combining fabrication accuracy and in-situ fine tuning) and use the same hardware to control both, routing the pulses with a nanosecond-timescale vector switch matrix. Despite the compromises required by this technique, we show a scalable path to single qubit control beyond the threshold required for quantum error correction. In benchmarking, we take into account gate leakage due to the fact that transmons are fundamentally multi-level systems. In the second experiment we establish entanglement between two transmon qubits on different chips. We use an entanglement by measurement scheme and demonstrate that we can overcome minor fabrication imperfections by shaping our measurement pulses. Ultimately, performance is mainly limited by photon loss between the chips and up to the amplification chain. This entanglement mediated by traveling photons could be used to make a distributed transmon processor where computations are spread across several chip modules. This modularity could enable connectivities that cannot be realized on chip and ease fabrication requirements, as modules could be individually fabricated and selected. Thus, both of these experiments fit into the larger effort to converge on the hardware, control equipment and architecture of a future large-scale transmon quantum computer. Other experiments I contributed to are summarized in the conclusion chapter to show the diverse physics that can be studied in cQED experiments.
The reproducibility of qubit parameters is a challenge for scaling up superconducting quantum processors. Signal cross talk imposes constraints on the frequency separation between neighboring qubits. The frequency uncertainty of transmon qubits arising from the fabrication process is attributed to deviations in the Josephson junction area, tunnel barrier thickness, and the qubit shunt capacitor. We decrease the sensitivity to these variations by fabricating larger Josephson junctions and reduce the wafer-level standard deviation in resistance down to 2%. We characterize 32 identical transmon qubits and demonstrate the reproducibility of the qubit frequencies with a 40 MHz standard deviation (i.e., 1%) with qubit quality factors exceeding 2 million. We perform two-level-system (TLS) spectroscopy and observe no significant increase in the number of TLSs causing qubit relaxation. We further show by simulation that for our parametric-gate architecture, and accounting only for errors caused by the uncertainty of the qubit frequency, we can scale up to 100 qubits with an average of only three collisions between quantum-gate transition frequencies, assuming 22%2 cross talk and 99.999.9%99.9 target gate fidelity.
The path toward practical superconducting quantum processors requires the integration of a large number of high-performance qubits. Modular architectures could offer a way to address the scaling limitations of monolithic designs by partitioning a large quantum processor into physically separated modules, or chiplets, linked through long-range interconnects. In this context, although fluxonium qubits have emerged as a compelling platform for quantum computing due to their long coherence times and high-fidelity gates, existing coupling schemes remain restricted to qubits in close proximity on a single chip. This limitation inherently precludes the long-range interconnects essential for modular integration. In this work, we propose a long-range tunable coupler designed to interconnect fluxonium qubits separated by more than one centimeter, thereby supporting the realization of modular fluxonium quantum processors. Under realistic assumptions, the proposed coupler has the potential to achieve inter-module two-qubit gate performance, specifically sub-100-ns gates with intrinsic errors below 10−410^{-4}10−4, comparable to that of intra-module (intra-chiplet) gates, while enabling modular integration with low quantum crosstalk, a key requirement for scalable systems. We further discuss the integration of this coupler into modular fluxonium lattices and explore its feasibility for achieving the higher connectivity and longer coupling range required for complex quantum error correction codes. This work could contribute to the development of large-scale fluxonium quantum processors by bridging their demonstrated potential with modular scalability.
The transmon, which has a short gate time and remarkable scalability, is the most commonly utilized superconducting qubit, based on the Cooper pair box as a qubit or coupler in superconducting quantum computers. Lattice and heavy-hexagon structures are well-known large-scale configurations for transmon-based quantum computers that classical computers cannot simulate. These structures share a common feature: a resonator coupler that connects two transmon qubits. Although significant progress has been made in implementing quantum error correction and quantum computing using quantum error mitigation, fault-tolerant quantum computing remains unachieved due to the inherent vulnerability of these structures. This raises the question of whether the transmon-resonator-transmon structure is the best option for constructing a transmon-based quantum computer. To address this, we demonstrate that the average fidelity of CNOT gates can exceed 0.98 in a structure where a resonator coupler mediates the coupling of three transmon qubits. This result suggests that our novel structure could be a key method for increasing the number of connections among qubits while preserving gate performance in a transmon-based quantum computer.
Superconducting transmon processors represent a leading platform for large-scale quantum computing due to their high gate fidelities and scalability. However, conventional qubit-coupler-qubit (QCQ) architectures face critical physical and structural bottlenecks, notably frequency crowding [spectator qubit collisions] during system scaling and inefficient mapping onto the standard surface code.To overcome these limitations, we propose a novel lattice-patch architecture that couples four fixed-frequency transmons to a single fixed-frequency coupler.This design enhances qubit connectivity and maps directly onto the surface-code lattice unit [plaquette], thereby minimizing the compilation overhead associated with logical qubit implementation. Furthermore, utilizing an entirely fixed-frequency design intrinsically eliminates susceptibility to external flux noise, ensuring robust operational stability.Multi-level numerical simulations demonstrate CNOT gate fidelities exceeding 0.98 across all six connectivity directions within the patch. Nevertheless, the complex interaction network of the four-qubit architecture induces unintended residual phase accumulation during cross-resonance driving. This parasitic effect necessitates precise calibration, achievable via virtual RzR_zRz​ gates [software phase updates]. Ultimately, our results establish the lattice-patch architecture as an efficient, robust building block for future fault-tolerant quantum computers.
As quantum computing advances toward fault-tolerance through quantum error correction, modular chiplet architectures have emerged to provide the massive qubit counts required while overcoming fabrication limits of monolithic chips. However, this transition introduces a critical compilation gap: existing frameworks cannot handle the scale of fault-tolerant quantum circuits while managing the noisy, sparse interconnects of chiplet backends. We present Chipmunq, the first hardware-aware compiler for mapping and routing fault-tolerant circuits onto modular architectures. Chipmunq employs a quantum-error-correction-aware partitioning strategy that preserves the integrity of logical qubit patches, preventing prohibitive gate overheads common in general-purpose compilers. Our evaluation demonstrates that Chipmunq achieves a 13.5x speedup in compilation time compared to state-of-the-art tools. By incorporating chiplet constraints and defective qubits, it reduces circuit depth by 86.4% and SWAP gate counts by 91.4% across varying code distances. Crucially, Chipmunq overcomes heterogeneous inter-chiplet links, improving logical error rates by up to two orders of magnitude.