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arXiv:2212.05493 · Journal of Applied Physics

Error suppression by a virtual two-qubit gate

Takahiro Yamamoto, Ryutaro Ohira

Published May 1, 2023• 9 citations
arXivHTMLPDF

Abstract

Sparse connectivity of a superconducting quantum computer results in large experimental overheads of SWAP gates. In this study, we consider employing a virtual two-qubit gate (VTQG) as an error suppression technique. The VTQG enables a non-local operation between a pair of distant qubits using only single qubit gates and projective measurements. Here, we apply the VTQG to the digital quantum simulation of the transverse-field Ising model on an IBM quantum computer to suppress the errors due to the noisy two-qubit operations. We present an effective use of VTQG, where the reduction in multiple SWAP gates results in increasing the fidelity of output states. The obtained results indicate that the VTQG can be useful for suppressing the errors due to additional SWAP gates. In our experiments, we have observed one order of magnitude improvement in accuracy for the quantum simulation of the transverse-field Ising model with 8 qubits. Finally, we have demonstrated an efficient implementation of the VTQG by utilizing dynamic circuits. This scheme reduces experimental overheads for implementing m VTQGs from O(10m) to O(6m).

DOI
10.1063/5.0151037

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Sparse connectivity of a superconducting quantum computer results in large experimental overheads of SWAP gates. In this study, we consider employing a virtual two-qubit gate (VTQG) as an error suppression technique. The VTQG enables a non-local operation between a pair of distant qubits using only single qubit gates and projective measurements. Here, we apply the VTQG to the digital quantum simulation of the transverse-field Ising model on an IBM quantum computer to suppress the errors due to the noisy two-qubit operations. We present an effective use of VTQG, where the reduction in multiple SWAP gates results in increasing the fidelity of output states. The obtained results indicate that the VTQG can be useful for suppressing the errors due to additional SWAP gates. In our experiments, we have observed one order of magnitude improvement in accuracy for the quantum simulation of the transverse-field Ising model with 8 qubits. Finally, we have demonstrated an efficient implementation of the VTQG by utilizing dynamic circuits. This scheme reduces experimental overheads for implementing m VTQGs from O(10m) to O(6m).
Abstract We show a certain kind of non-local operations can be simulated by sampling a set of local operations with a quasi-probability distribution when the task of a quantum circuit is to evaluate an expectation value of observables. Utilizing the result, we describe a strategy to decompose a two-qubit gate to a sequence of single-qubit operations. Required operations are projective measurement of a qubit in Pauli basis, and π/2 rotation around x, y, and z axes. The required number of sampling to get an expectation value of a target observable within an error of ϵ is roughly O(9 k /ϵ 2), where k is the number of ‘cuts’ performed. The proposed technique enables to perform ‘virtual’ gates between a distant pair of qubits, where there is no direct interaction and thus a number of swap gates are inevitable otherwise. It can also be utilized to improve the simulation of a large quantum computer with a small-sized quantum device, which is an idea put forward by Peng et al (2019 arXiv: 1904.00102 ). This work can enhance the connectivity of qubits on near-term, noisy quantum computers.
We experimentally demonstrate a virtual two-qubit gate and characterize it using quantum process tomography (QPT). The virtual two-qubit gate decomposes an actual two-qubit gate into single-qubit unitary gates and projection gates in quantum circuits for expectation-value estimation. We implement projection gates via midcircuit measurements. The deterministic sampling scheme reduces the number of experimental circuit evaluations required for decomposing a virtual two-qubit gate. We also apply quantum error mitigation to suppress the effect of measurement errors and improve the average gate fidelity of a virtual controlled- Z (CZ) gate to fav=0.9938±0.0002 . Our results highlight a practical approach to implement virtual two-qubit gates with high fidelities, which are useful for simulating quantum circuits using fewer qubits and implementing two-qubit gates on a distant pair of qubits. Published by the American Physical Society 2024
Coherent errors, and especially those that occur in correlation among a set of qubits, are detrimental for large-scale quantum computing. Correlations in noise can occur as a result of spatial and temporal configurations of instructions executing on the quantum processor. In this paper, we perform a detailed experimental characterization of many of these error sources, and theoretically connect them to the physics of superconducting qubits and gate operations. Equipped with this knowledge, we devise compiler strategies to suppress these errors using dynamical decoupling or error compensation into the rest of the circuit. Importantly, these strategies are successful when the context at each layer of computation is taken into account: how qubits are connected, what crosstalk terms exist on the device, and what gates or idle periods occur in that layer. Our context-aware compiler thus suppresses some dominant sources of error, making further error mitigation or error correction substantially less expensive. For example, our experiments show an increase of 18.5%\mathbf{1 8. 5 \%}18.5% in layer fidelity for a candidate 10 -qubit circuit layer compared to context-unaware suppression. Owing to the exponential nature of error mitigation, these improvements due to error suppression translate to several orders of magnitude reduction of sampling overhead for a circuit consisting of a moderate number of layers.
High fidelity quantum operations are key to enabling fault-tolerant quantum computation. Superconducting quantum processors have demonstrated high-fidelity operations, but on larger devices there is commonly a broad distribution of qualities, with the low-performing tail affecting near-term performance and applications. Here we present an error budgeting procedure for the native two-qubit operation on a 32-qubit superconducting-qubit-based quantum computer, the OQC Toshiko gen-1 system. We estimate the prevalence of different forms of error such as coherent error and control qubit leakage, then apply error suppression strategies based on the most significant sources of error, making use of pulse-shaping and additional compensating gates. These techniques require no additional hardware overhead and little additional calibration, making them suitable for routine adoption. An average reduction of 3.7x in error rate for two qubit operations is shown across a chain of 16 qubits, with the median error rate improving from 4.6%\%% to 1.2%\%% as measured by interleaved randomized benchmarking. The largest improvements are seen on previously under-performing qubit pairs, demonstrating the importance of practical error suppression in reducing the low-performing tail of gate qualities and achieving consistently good performance across a device.
Accurate assessment and management of errors is indispensable for extracting useful results from noisy intermediate-scale quantum devices. In this work, we propose the qubit error probability (QEP), a device specific metric that combines relaxation, dephasing, gate, and measurement contributions into a single per qubit figure of merit computable before execution. Leveraging QEP as the control variable, we revisit zero noise extrapolation (ZNE) by adding pairs of controlled native two-qubit gates on all connected qubit pairs to generate circuits with successively larger mean QEP; the zero error limit is then approximated by a linear regression of the measured observable against those values. Benchmarking on IBM Quantum Heron processors, we apply QEP guided ZNE to first order Trotterized simulations of the two dimensional transverse field Ising model, chosen as a representative interacting many body system, involving up to 68 qubits and 15 Trotter steps. In regimes where the raw circuits exhibit a finite mean QEP, the method suppresses observable errors beyond those attainable with circuit depth scaled ZNE, while requiring only three noise scaled evaluations and no additional classical post processing. These results demonstrate that QEP serves as a transparent and efficient error metric and that its integration into ZNE provides a practical route to reliability gains on current superconducting hardware, without the resource costs associated with full quantum error correction.
We present a simple, malleable and low-overhead approach for improving generic biased quantum error mitigation (QEM) methods, achieving up to 15% fidelity improvements over standard QEM on 100-qubit circuits with up to 2000 entangling gates. We do so by constructing verifiable benchmark circuits which mirror the application circuit's native-gate structure and thus noise profile. These circuits can be used to benchmark and mitigate the bias of the underlying error mitigation method, requiring only the application circuit and hardware native gate set. We present two methods for generating benchmark circuits; one is agnostic to the target hardware at the expense of a small overhead of single-qubit gates, while the other is specific to the IBM superconducting hardware and has no gate overhead. As a corollary, we introduce benchmarked-noise zero-noise extrapolation (bnZNE) as a simple adaptation of zero-noise extrapolation (ZNE), one of the most popular error mitigation methods. We consider as an example the bias-mitigated ZNE and bnZNE of Trotterized Hamiltonian simulations, observing that our approaches outperform standard ZNE using both small-scale classical simulations and 100-qubit utility-scale experiments on the IBM superconducting hardware. We consider the measurement of both single-site observables as well as two-site correlations along a one-dimensional qubit chain. We also provide a software package for implementing the error mitigation techniques used in this research.